BLITTER RE-CREATION THOUGHTS

Progress on our FPGA cores.
keli
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Re: BLITTER RE-CREATION THOUGHTS

Post by keli » Tue Nov 05, 2019 7:36 pm

exxos wrote:
Tue Nov 05, 2019 5:01 pm
Sure its a FlipFlop, but why 2 clock inputs, They are just C and /C driven by a inverter elsewhere. Normally C would latch on the falling edge, and /C Would latch on the rising edge. But this one has both. I've noticed this funkyness all over with other blocks as well. I think only 1 clock is needed, but no way to know what edge its supposed to latch on :shrug:
Well I guess it's some sort of differential clock flip flop. Probably a implementation detail of the original design...
But since the falling edge of C coinsides with the rising edge of /C, I don't see a problem here. The answer to your question is "both" :P ... It latches on the falling edge of C, which is also the rising edge of /C.

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Re: BLITTER RE-CREATION THOUGHTS

Post by exxos » Tue Nov 05, 2019 7:50 pm

keli wrote:
Tue Nov 05, 2019 7:36 pm
Well I guess it's some sort of differential clock flip flop. Probably a implementation detail of the original design...
But since the falling edge of C coinsides with the rising edge of /C, I don't see a problem here. The answer to your question is "both" :P ... It latches on the falling edge of C, which is also the rising edge of /C.
Theres 2 points in the cycle I can latch though, I can latch on the rise or the fall.... with the differential logic, "both" can be the start of the transition, or both on the end of the transition. :stars:
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Re: BLITTER RE-CREATION THOUGHTS

Post by exxos » Tue Nov 05, 2019 8:36 pm

Looks like such things actually exist...

https://www.onsemi.com/pub/Collateral/MC100LVEL51-D.PDF
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Re: BLITTER RE-CREATION THOUGHTS

Post by exxos » Sun Nov 10, 2019 1:05 pm

Looking at the STE's combel, it looks like only "C" is even connected.

Capture.PNG
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I have started to re-create the logic blocks in the blitter in Quartus and Icky has started doing the leg work in linking it all up. Are we insane ? Probably yes :lol: but we doing it anyway. But learning how the blitter works and re-creating it makes a long, but interesting project.

I am making them as close to the original as possible. So this will be a literal gate copy design. This will mean we *should* have a 100% replica of the blitter on a gate level. Well, maybe not 100% as I am having to remove the differential logic in some places, but that aside, its function should be exactly as the original.

The Ricoh datasheet has these options for PLCC68

Capture2.PNG
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So the gate count must be one of, 2300,2900,3800.

I am wondering if it would fit inside a ATF1508 5V PLD.. Though I can't seem to find a "gate count" on those devices. I would assume modern PLD's would have higher specs than the Ricoh's had. If we could fit it into a ATF PLD, that would mean no FPGA needed for the blitter and we can likely add other stuff into the same PLD as well.

Of course this will be ongoing in the background for a while as its not a main project at the moment. Though we haven't given up with this project :)
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Re: BLITTER RE-CREATION THOUGHTS

Post by Icky » Sun Nov 10, 2019 1:10 pm

exxos wrote:
Sun Nov 10, 2019 1:05 pm
I have started to re-create the logic blocks in the blitter in Quartus and Icky has started doing the leg work in linking it all up. Are we insane ? Probably yes :lol: but we doing it anyway. But learning how the blitter works and re-creating it makes a long, but interesting project.
We are quite probably bonkers but as you say its an interesting learning experience and if it works then we are as close to 100% as we can possibly be.

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Re: BLITTER RE-CREATION THOUGHTS

Post by exxos » Sun Nov 10, 2019 1:16 pm

Icky wrote:
Sun Nov 10, 2019 1:10 pm
We are quite probably bonkers but as you say its an interesting learning experience and if it works then we are as close to 100% as we can possibly be.
Yeah, advantage of we can maybe add in other stuff like IDE or TOS206 decoding etc.

Looking around the web I did find "Atmel ATF1508-15 CPLD chip is compatible with Altera MAX 7128, containing 128 microcells over 2500 usable gates" So we should in theory match the 2300 Rioch gate count on that one. I'm sure I saw a image of the blitter with chip number on the mask somewhere the other day :shrug: In anycase, I would assume our gate count to be a fraction lower than the original. I guess it depends how well Quartus translates it all.
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Re: BLITTER RE-CREATION THOUGHTS

Post by czietz » Sun Nov 10, 2019 1:52 pm

I don't want to disappoint you, but you'll need a way bigger device than a 128 register CPLD to fit the Blitter. Even the halftone RAM alone takes more than 128 registers.

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Re: BLITTER RE-CREATION THOUGHTS

Post by exxos » Sun Nov 10, 2019 2:01 pm

czietz wrote:
Sun Nov 10, 2019 1:52 pm
I don't want to disappoint you, but you'll need a way bigger device than a 128 register CPLD to fit the Blitter. Even the halftone RAM alone takes more than 128 registers.
Not disappointed as didn't expect it would fit anyway. Though the Ricoh doesn't seem to list number of registers, only gates.
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Re: BLITTER RE-CREATION THOUGHTS

Post by Icky » Sun Nov 10, 2019 3:23 pm

BLT CELL reconstructed

Screenshot 2019-11-10 at 15.22.00.png
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Re: BLITTER RE-CREATION THOUGHTS

Post by exxos » Sun Nov 10, 2019 9:25 pm

plus what is inside each block...

Capture.JPG
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4MB STFM 1.44 FD- VELOCE+ 020 STE - 4MB STE 32MHz - STFM 16MHz - STM - MEGA ST - Falcon 030 CT60 - Atari 2600 - Atari 7800 - Gigafile - SD Floppy Emulator - PeST - HxC - CosmosEx - Ultrasatan - various clutter

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