BLITTER RE-CREATION THOUGHTS

General discussions or ideas about hardware.
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exxos
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Re: BLITTER RE-CREATION THOUGHTS

Post by exxos » Thu Sep 13, 2018 2:51 pm

rpineau wrote:
Thu Sep 13, 2018 2:49 pm
For the pull-up I found this in the datasheet :
Internal Weak Pull-Up Resistor:
All I/O pins, except configuration, test, and JTAG pins, have an option to enable weak pull-up.
ahhh yes, I forgot about the internal FPGA pull ups! That would solve any potential issues.
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Re: BLITTER RE-CREATION THOUGHTS

Post by exxos » Thu Sep 13, 2018 8:09 pm

I've put together a little buffer test board.. Will likely be a couple of weeks while the CVs arrive..I think is best to actually check out the real world chip before investing in building up the actual blitter pcbs..

There should not be any issues, but knowing my luck...

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Re: BLITTER RE-CREATION THOUGHTS

Post by Stimpy » Fri Sep 14, 2018 9:43 am

exxos wrote:
Thu Sep 13, 2018 12:32 pm
After talking to Rodolphe we realise that the suska code won't play nice with external buffers :roll:

Wolfgang says the blitter is a "drop in replacement" which it is, BUT, only if using a 5V FPGA, which doesn't exist. Which means using external buffers is the way to go, BUT, suska blitter doesn't output any signals to control external buffers, so this has put a huge spanner in the works :roll:
:roll: You can probably use the WF101643IP_TOP_SOC instead of WF101643IP_TOP.

Three groups of buffers, one for Address Bus, one for Data Bus and the other for Control (DRACK, RW, AS, LDS, UDS, FC).
If the enable line (ADR_EN or DATA_EN or BUSCTRL_EN) is high, enable the bus transceivers. Perhaps you need to flip the logic level to make it an active low signal, something like this perhaps:

output <= not input;

The BR and BGACK outputs seem to just be open drains.

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Re: BLITTER RE-CREATION THOUGHTS

Post by exxos » Mon Oct 22, 2018 8:56 pm

My test buffer PCB arrived.. So will try and build this up and give it a try out..

Really this is just double checking that when the 3.3V side goes tri-state, that it does not affect the 5V side. I don't think that it will, but I'm going to try this out on breadboard once assembled up is to make sure before I get the full blitter PCBs made.

These chips to the 3<>5 translation automatically.. Really also happens is both sites have a pull-up resistor, and if either side goes low, the other side goes low. So really simple stuff.

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Re: BLITTER RE-CREATION THOUGHTS

Post by exxos » Mon Oct 22, 2018 9:39 pm

Man, these chips are tiny! :lol:

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Re: BLITTER RE-CREATION THOUGHTS

Post by exxos » Mon Oct 22, 2018 10:22 pm

So my findings are firstly a diode doesn't drop enough voltage and ends up being 4.2V not 3.3V, so a regulator be better really on these things..

5V isn't 5V output, ends up 4.2V.. 3.3V should still be able to drive a logic 1 on a 5V rail anyway..

Main problem is when the 3.3V side isn't connected to anything, the voltage on that pin floats up to 5V :roll: So basically what this would mean would be that when the FPGA went tri-state, that input pin would actually float up to 5Volts.. And I assume would actually damage the FPGA with it being a 3.3V device..

However the FPGA does have weak pullups internally, but I'm still not really happy about this idea now.. I guess it depends if they are enabled all the time even when tri-stated, and exactly how much pull-up current they have...

EDIT:

I guess if the 3.3V bus was always driving the the 5V bus then there wouldn't be any problems.. but how it is, you would think the 3.3V side would always actually be 3.3V.. I don't get it... :roll:

I've sent a email to IDT explain this... It seems to defeat the object of the thing if a tri-stated 3.3V devices ends up being driven with 5V!
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Re: BLITTER RE-CREATION THOUGHTS

Post by exxos » Thu Oct 25, 2018 8:19 pm

No word back from IDT :roll:

But I'm pretty sure these chips you do not work correctly without a pull-up resistor on the 3.3V side. :roll: Ironically these chips just act like a wire link between input and output. So when nothing is connected on the 3.3V side, and you have 5 V on the input side, 5 V literally goes across the chip to the 3.3V output. Unfortunately I just simply do not have space to add in like 60 pull-up resistors.

Am really considering just giving up with these chips. I still don't really know what would happen in a tri-state situation either.

I am thinking even though it would be a rather a lot of parts count to do this, that if I was neading the pullups anyway, I could use a zener and a diode to take care of the voltage interfacing. It would actually be cheaper than the chip, and likely easier to solder, but of course uses a lot more parts.

What I am really thinking is of designing a small voltage translator board, which can be used on multiple projects. This way there would actually be a stacked PCB arrangement, where the FPGA chip would be on its own PCB which would plug into the PLCC socket (for example) and it would have header pins for connecting to the logic level shifter boards (would likely be 4 of such boards).

If we did not have to worry about tri-state, then pretty much any general logic level translator chip would work. In case of the blitter, it needs to be tri-stated and it does not have control logic in the core to take care of that.

So I think things simple, and without messing about, I will probably look into not using translator chips for this..Those IDT chips do seem like a lot more trouble than they are worth. With them basically costing £1 each (£4 total) backup probably be enough to assemble a lot of discrete parts anyway.
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Re: BLITTER RE-CREATION THOUGHTS

Post by Stimpy » Thu Oct 25, 2018 8:29 pm

The 5v you see on the pin is probably just leakage current and the tiny ESD diodes inside the FPGA will just clamp that, it'll be microamps.

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Re: BLITTER RE-CREATION THOUGHTS

Post by Stimpy » Thu Oct 25, 2018 8:32 pm

exxos wrote:
Thu Oct 25, 2018 8:19 pm
If we did not have to worry about tri-state, then pretty much any general logic level translator chip would work. In case of the blitter, it needs to be tri-stated and it does not have control logic in the core to take care of that
The suska code does if that's what you mean? My post from 14th september describes how to use it.

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Re: BLITTER RE-CREATION THOUGHTS

Post by exxos » Thu Oct 25, 2018 8:35 pm

Stimpy wrote:
Thu Oct 25, 2018 8:32 pm
The suska code does if that's what you mean? My post from 14th september describes how to use it.
The code trisates the FPGA pins yes, but that assumes a 5V FPGA, which I can't find. So it has to have voltage translation buffers.. which then have no way to tristate... I was talking to wolfgang about that, but I dont think he understands what I mean.
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