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Posted: Tue Aug 22, 2017 10:37 pm
by exxos
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Many should know the great work over at in recovering some lost Atari files. I saw in there 2 versions of the blitter IC. 1986 and 1988. I did not see much difference between the 2 files other than some "double inverters" for example. Mostly I assume Atari did that for a extra delay on some signals. Though while that is probably true to a point, I also see double inversions on some address and data lines. The only reason I can think of doing that, other than the delay, is to clear up noise issues.. so here we go again..

Going back to my researching into some blitters not working on the MEGA ST, the notes I saw basically tally to the year of 1988. Where blitters before that date would have issues in the MEGA ST. Ones dated later than 1988 would work fine.

What caught my attention is the Atari blitter being dated 1986 which must be the blitter which is "buggy" on the MEGA ST. which means 2 years later in 1988 , Atari noticed the problem, updated the blitter to "cure" those issues. So a new blitter was born.

It is hard to say exactly whats going on. For starters we have the "blitter patch" in the MEGA. As noted on my site some time ago, I have been removing that "patch" and so have others and nobody I know of has had any isuses. This could mean those earlier blitters needed the patch and the later ones didn't. Though I think there is more than one issue going on as usual.

It could be the blitter was updated to fix some issues in the STE for example. Though later the blitter fails in the MEGA ST, So Atari do the "blitter patch" to solve it. Mostly this seems to be down to manufacture of the blitter. Though with little date to go on, its difficult to form any conclusions. Though its clear in any case, Atari must have had some noise issues on some machine in 1988 in order that they updated the blitter.

In anycase, as there is a 2 year gap with basically no changes, I am assuming the blitter schematic is a final one. Which gives me a thought to cloning it in a modern PLD.

Looking into it some more, it gets confusing as to what is going on.. Take this for example..
Capture2.PNG (38.49 KiB) Viewed 2836 times
We basically have a clocked flipflop by the looks of it. Only it has a clock and a inverted clock. The orange route shows "clock" and the green route "X clock" or "NOT Clock". This doesn't really make any sense as to what or why that is done. I can only assume that the PLD used by Atari needed the design doing that way for some reason. Maybe the software back in the 80's needed all inputs to be connected to something, even if it was totally pointless.
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Similar there seems to be a tri-state buffer, giving dual outputs, feeding a inverter with dual inputs. I mean, for the love of god, WHY?! To make it even more pointless, another double inversion at the end of the chain.

I can only assume here, again, both enable and NOT enable have to be wired up. I'm also assuming the square OPAD is a output pad. Then it would make more sense that there is a tri-state buffer with a simple inverter on it.

We also have the 2 inverters which lead of to AI23. I assume here that the OPAD actually is wired to A23 on the 68000 bus.. Double inversion, no idea, probably just to add some buffered delay there.

On the left we have AO23, So assume Address Output 23, which would make sense going to a PLD IO pin. So really AI23 is just a feedback node from the 68000 bus.

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Then we have logic blocks such as P7008. I can only assume it is a 1 of 2 multiplexer. SA and SB are same signal inverted. So that would actually be a SELECT line to select A or B inputs. Again it doesn't really make sense why there would be 2 select lines needing the inverter. Again I assume its just some "primitive" stuff going on in early the PLD design software. If all that "logic" was taken out, the whole circuit would be a lot simpler.

If I can figure all this out, then there is no reason why this diagram can't be ported over to a Altera PLD and compiled into a new chip. With blitters getting harder to find and only FPGA clones which are likely not 100% cycle correct, then cloning the blitter is at least a backup for the future. It would also mean low cost blitters could be created for STFM machines I think a 100% compatible hardware clone can only be a good thing.



Posted: Thu Aug 24, 2017 10:05 am
by keli
I've been scratching my head over these schematics as well. The STE glue/MMC combo schematics contain similar weirdnesses.

I think you're right in assuming the multiple inverters were added to fine-tune timing issues and as buffers for fan-out of some signals. (Even though a buffer would have done the same. Maybe the designers were exploiting the timing differences somehow?)

I noticed that the "ML2" in your first capture is actually a macro expanded on the last sheet along with other cells.
ML2.png (4.22 KiB) Viewed 2829 times
The actual flip flop still uses something that looks like a differential clock. Maybe it's designed to load the value on both edges of the "clock", basically doubling the frequency of updates? Note that the TQ output is actually a tri-stated version of Q (fed from XQ via an inverted input for some reason!!)

Also I think you're right in your assumption that the square named "PAD" is a physical pad on the chip. The A23 signal must only be driven when the blitter has the bus and wants to emit an address, but the blitter also needs to read from the very same pin when the CPU has the bus and wants to access one of its registers, therefore the AI23 signal is connected to the other side of the weird tri-state setup. -- Even though it'll get the same value as the AO23 wire when it's enabled, it will also be able to read values coming from the outside.

For the multiplexer, I've guessed that the SA and SB input stand for "select A" and "select B". I guess that there are two selection inputs to allow the output to be high-Z when neither are selected. God knows what would happen when both SA and SB are high.


Posted: Thu Aug 24, 2017 10:18 am
by exxos
I was talking to the chap who found the schematics a few weeks ago. We basically concluded that "back in the day" the outputs to the PLD's were actually inverters (they are larger than actual inverters). So this would mean Atari would have had to place another inverter in series to keep a "1 in 1 out". In modern PLD's this isn't shown anymore, so we don't actually "need" those "double inverters". This makes the circuit a lot easier to understand then.

Also , not sure about modern PLD's, but a lot of stuff I think you have to treat more like "open collector" type logic, when "driving low" is a lot stronger than driving a logic 1. So its probably why the larger inverters are shown (as pin outputs). Mostly the databus is pulled up with resistors, so it makes sense the main drive current is in logic lows.

It also seems Atari had issues internally and added in some "double inverters" as the internal logic seemed to be having issues. Plus I think they had noise from the motherboard bus to cope with (no surprise there). So again we can actually back track a blitter version and "use" the simpler circuit.

It also seems "back in the day" PLD logic needed those odd differential inputs, like driving high and low clocks, or inverted and non-inverted signals. this just isn't needed anymore. We just need 1 clock and 1 input. So again the circuit can be simplified a lot once all that "clutter" is removed.

I think overall, if a new PLD circuit is designed, I don't think it would have half the parts as shown in the original schematic. I think it would fit easily in a chip like the Altera where the circuit could pretty much be copied over. I mean modern PLD's are a lot more advanced than in the 80s. We could probably fit the blitter into a PLD 100 times over :lol:


Posted: Tue Oct 31, 2017 5:16 pm
by exxos
I was actually thinking today, that a gate level blitter isnt really needed. The speed is basically limited by the RAM speed anyway.

Really do wonder if anyone out there take code from the MiST or Suska HDL files and adapted so it would work as a standalone replacement blitter IC ?

I have considered this before, but the price of IC plus the PCB and assembly etc all added up to be quite expensive. Though obtaining new blitter chips has become very difficult recently. So recreating the blitter in a PLD/FPGA would be the only way to go.


Posted: Tue Apr 03, 2018 1:49 pm
by exxos
Looking at the diagrams again..

Assuming here its literally a bank and AND gates feed into a 5 input NOR gate and that its just "drawn funny" in "80's style" tech...

andnor.jpg (21.6 KiB) Viewed 2483 times

Also this type of thing going on...
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Problem is, are those "double inversions" really needed... Logic wise they do nothing, but would add a delay.. but no way to know if that delay is needed or not.. Though I would suspect the PLD compiler would remove the double inversion anyway.. :shrug:

There is also the issue of active high or low levels...
sab.jpg (19.46 KiB) Viewed 2480 times
When SA is high , is that channel selected or de-selected :shrug:


Posted: Tue Apr 03, 2018 3:54 pm
by troed
exxos wrote:
Tue Oct 31, 2017 5:16 pm
Really do wonder if anyone out there take code from the MiST or Suska HDL files and adapted so it would work as a standalone replacement blitter IC ?
AFAIK the Suska was developed IC for IC, where the VHDL version was always tested drop-in on a regular ST motherboard and so should be 100% pin and signal compatible. I haven't looked at the code to see if it's easy to extract a single IC part again though.


Posted: Tue Apr 03, 2018 4:04 pm
by exxos
troed wrote:
Tue Apr 03, 2018 3:54 pm
AFAIK the Suska was developed IC for IC, where the VHDL version was always tested drop-in on a regular ST motherboard and so should be 100% pin and signal compatible. I haven't looked at the code to see if it's easy to extract a single IC part again though.
It is all separate files...
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I've not checked if all the pins are there or not..


Posted: Tue Apr 03, 2018 6:22 pm
by exxos
Lets try and compile it...

Oddly seems to have compiled right off.. :shrug: That was to easy :shrug: :shrug:

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So I tried a MAX II 240 device.. it wont have it...

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Was looking at 3.3V devices and "low cost" chips.. will keep looking...

MAX 570 device... nope..
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OK so Cyclone 1 is next.. but Quartus 13 was last support (using V17 atm) so good job I still have it installed!.. OK it only has cyclone II listed :pullhair: and Quartus 13 just refuses to behave and complains every step of the way.. so might just be easier to go with the later cyclone versions as I think V13 is just buggy..


Dang it!
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2a.jpg (9.91 KiB) Viewed 2436 times

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Only problem is this is a BGA.. and the TQFN hasn't got enough logic blocks :roll:

Onto the MAX 10 series...
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So the 10M02SCE144I7G seems doable for the smallest/cheapest chip.. ... YQnA%3d%3d

To be continued...


Posted: Tue Apr 03, 2018 7:50 pm
by exxos
So here is the schematic block.. looks so innocent.. At that point I know how to wire pins up to it (just have to unforget first :twisted: )

blitsym.jpg (16.44 KiB) Viewed 2430 times


Posted: Tue Apr 03, 2018 9:35 pm
by Stimpy
Might be best to use the latest tools and latest series of cyclone, 4 or 5. Might cost a bit more but will give you more room to add things and the speed will be greater as the routing won't be so complex and they are made on a smaller die process. You also get nice things like DDR controllers, larger block ram etc. Also don't be put off by BGA as tqfp is dead for FPGAs, same goes for 5v logic levels. 1.0mm BGA is pretty easy to route and as you don't need much IO you can just use the outer connections and route straight out. You'll need decent decoupling as the edge rate on the IO drivers can be very fast so 0402 caps good idea.