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Microscopic chip analysis

Posted: Tue Dec 11, 2018 12:59 am
by sandord
I saw this tweet today:


The GDG is the Sharp MZ-800's equivalent of the ST's glue/mmu/shifter (don't know exactly the mixture)

I wondered if this technique could help us get less dependent on original custom chips from Atari... I have no idea how they can use pictures like that to analyse chip behaviour, let alone creating a clone of it. But it's amazing still...

Posting the picture here, in case the link goes dead in the future:

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Re: Microscopic chip analysis

Posted: Tue Dec 11, 2018 6:41 am
by czietz
ijor has been reverse-engineering Atari ASICs in this way for years. Look at the extensive information he posted at Atari-forum.com.

Re: Microscopic chip analysis

Posted: Tue Dec 11, 2018 7:19 am
by czietz
See for examples these threads:
http://atari-forum.com/viewtopic.php?f=16&t=29658
http://atari-forum.com/viewtopic.php?f=15&t=30241

Or this blog post that contains a die shot of the ST MMU contributed by ijor:
https://www.fpgaarcade.com/back-to-scho ... die-shots/

Re: Microscopic chip analysis

Posted: Tue Dec 11, 2018 8:51 am
by exxos
I think I talked about it on here about a year ago. I looked into the actual cost of getting it done, basically sell off a couple of your spare houses to fund it. A lot of companies only do more known chips as well.

I think there is a video somewhere of how they do it. I think they take the top off the chip, take a ultra-high-res capture of the die, then run it though special software which identifies the die parts and converts them into logic blocks. Basically can get a schematic from it.

Re: Microscopic chip analysis

Posted: Tue Dec 11, 2018 10:38 am
by sandord
Oh wow, this explains how the current state of emulators and fpga-implementations is as good as they are.

I guess that eventually, all secrets will be uncovered this way. If smaller fpgas become available, drop-in replacements of the chips might even be possible but I guess it will always be more expansive than a single fpga that emulates all of them.

I'm aware I'm regurgitating subjects that have been talked about many times, it's just the subject that sparked my curiosity.

Re: Microscopic chip analysis

Posted: Tue Dec 11, 2018 10:49 am
by exxos
AFAIK nothing has been reversed engineered in the ST chipset, at least not fully. The only thing we really have is the blitter diagrams. I was going to make a gate level version, but thought just using the suska code be less painful as should do the same job. It takes serious money to reverse engineer a chip.

Re: Microscopic chip analysis

Posted: Tue Dec 11, 2018 1:10 pm
by ijor
Decapping and reverse engineering old school chips is my favorite hobby :)
One interesting place to visit is visual 6502.
sandord wrote: Tue Dec 11, 2018 10:38 amIf smaller fpgas become available, drop-in replacements of the chips might even be possible but I guess it will always be more expansive than a single fpga that emulates all of them.
Drop-in replacements are available already for several systems. Mark (Foft at various forums) recently released Pokeymax, the Atari 8-bit sound chip also used in some arcade systems. The main problem is usually not exactly the size of the fpga itself, but the need of voltage level shifters.

Yes, a single FPGA would be much better and in some cases it might not even need the level shifters.
exxos wrote: Tue Dec 11, 2018 10:49 amAFAIK nothing has been reversed engineered in the ST chipset, at least not fully. The only thing we really have is the blitter diagrams.
I reverse engineered the whole ST chipset and several other chips including the 68000. That's why I could release cycle accurate FPGA cores. Smonson Shifter re implementation is also based on my reverse engineering work.

There was no need to reverse engineer Blitter. Christian recovered the original schematics.

Re: Microscopic chip analysis

Posted: Tue Dec 11, 2018 1:20 pm
by exxos
ijor wrote: Tue Dec 11, 2018 1:10 pm I reverse engineered the whole ST chipset and several other chips including the 68000. That's why I could release cycle accurate FPGA cores. Smonson Shifter re implementation is also based on my reverse engineering work.
So is there proper logic diagrams of the GLUE, MMU etc then ?

Re: Microscopic chip analysis

Posted: Tue Dec 11, 2018 4:31 pm
by ijor
exxos wrote: Tue Dec 11, 2018 1:20 pm
ijor wrote: Tue Dec 11, 2018 1:10 pmI reverse engineered the whole ST chipset and several other chips including the 68000.
So is there proper logic diagrams of the GLUE, MMU etc then ?
I didn't release full schematics yet. You said that "nothing has been (fully) reversed engineered in the ST chipset", and that is not true. You don't necessarily need schematics for reversing (and for that matter, you don't need to release them). I consider HDL code much more convenient than schematics, especially if it is properly commented. Btw, when you hire one of those companies that charge you 5 figures to reverse each chip, they don't deliver schematics, they deliver a simple flat netlist, not even HDL.

The main (only) reason I try to produce schematics is because for many people it's easier to understand. Producing the schematics involves some artistic work well beyond the reversing. Anyway, I released almost complete schematics of Shifter already. Shifter arguably might be the most interesting chip at this point that GSTMCU original schematics were recovered.