STE V2 BOOSTER + SRAM STATUS

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STE V2 BOOSTER + SRAM STATUS

Post by exxos » Mon Nov 20, 2017 4:15 pm

Started this today..

Based on the V1.5 plug in booster design.. This one sees the addition of a large PLD to take care of the SRAM decoding. I'm routing all the address and databus to the PLD.. not sure why..

In anycase, 2MB per IC, 8MB Fast-Ram going on. Had to use 5<>3.3V IO translators as the SRAM's are all 3.3V these days. RAM will be accessed at 32MHz.

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Re: STE V2 BOOSTER + SRAM STATUS

Post by arf » Mon Nov 20, 2017 6:05 pm

exxos wrote:
Mon Nov 20, 2017 4:15 pm
Based on the V1.5 plug in booster design.. This one sees the addition of a large PLD to take care of the SRAM decoding. I'm routing all the address and databus to the PLD.. not sure why..

In anycase, 2MB per IC, 8MB Fast-Ram going on. Had to use 5<>3.3V IO translators as the SRAM's are all 3.3V these days. RAM will be accessed at 32MHz.
:cheer: That sounds interesting!
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Re: STE V2 BOOSTER + SRAM STATUS

Post by exxos » Mon Nov 20, 2017 8:51 pm

....sometime later....

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... and to think i've been working on this non-stop since my previous post...
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Re: STE V2 BOOSTER + SRAM STATUS

Post by exxos » Mon Nov 20, 2017 10:11 pm

Getting there...
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... Space in the top left for some Flash as well it seems ;)
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Re: STE V2 BOOSTER + SRAM STATUS

Post by exxos » Wed Nov 22, 2017 1:44 pm

6 more hours spent on it today.. got flash added...

Need to add a small flash for a config register next.. bit more tricky that...
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Re: STE V2 BOOSTER + SRAM STATUS

Post by exxos » Thu Nov 23, 2017 4:41 pm

Been giving thought to storing booster options when the machine is first powered up and down..

I was thinking of using a small EEPROM to store the booster settings, but this seems to be a total waste of a IC.

As there is actually flash on the board anyway, I was thinking about using the very last eight bits in the flash memory for the storage register. Of course this means the last eight bits in the last ROM bank would not be able to be used by the ROM, should not really be a problem as long as the checksum data is not there or something..

In any case, the address bus on power up will all be 1's, due to the pullups on the CPU. I can use that to select the upper ROM bank in the flash on power up. The PLD I can set the ROM bank select bits to 11 to also select the upper ROM bank and enable the flash to output data onto the databus.

At this point the machine is still in reset and nothing yet has happened. Other than data is now actually on the bus. When the reset signal changes I can use that signal to latch the data on the bus inside the PLD which in turn loads control bits of the booster functions. At the same time the reset signal will be used to disable the flash bank, the databus will be pulled high, and the machine will now start the power up sequence as normal.

The only problem here, is that I do not think just 8 bits can be programmed with a EEPROM.. I need to look into this a bit more as I have never used flash or EEPROM before....

EDIT:

ok both eeprom and flash can't really do a single byte update :(

Byte-Program Operation
The SST39SF010A/020A/040 are programmed on a byte-by-byte basis. Before programming, the sector
where the byte exists must be fully erased.

Sector-Erase Operation
The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The
sector architecture is based on uniform sector size of 4 KByte. The

So looks like I will have to go for a separate IC or sacrifice a ROM bank... I guess even 3 out of 4 ROM's is still good really though..
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Re: STE V2 BOOSTER + SRAM STATUS

Post by exxos » Thu Nov 23, 2017 7:53 pm

Urban is working on the solution with a ATINY IC. Basically a small 14 pin SOIC package. Should be to use it as single byte flash register..

Basically this new booster can be configured hardware switches like the previous STE booster, or it can be configured for software control, which is where the flash register comes in.

The ROM selection bank select is also stored in the register. So 2 bits will be used for ROM select, another bit for booster on or off. A fourth bit will be used for a write enable line for the flash ROM. I don't think any other things really need configuring.. Less I have forgotten something... Even so there are still be 4 bits left over currently.
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Re: STE V2 BOOSTER + SRAM STATUS

Post by exxos » Fri Nov 24, 2017 3:26 pm

Several hours later...

ATTINY added for the booster register, also just had enough IO pins for IDE.

2417.JPG
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Need to start adding some caps on there somewhere next... and the jtag header could be a problem :roll:
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Re: STE V2 BOOSTER + SRAM STATUS

Post by exxos » Fri Nov 24, 2017 7:24 pm

Still routing...

Program header now added.. Was a nightmare to matching the routing for it :roll:

Finally added the regulator as well for 3.3V stuff... Also had to shift around a lot of traces as it was breaking the power rail routes :roll:

I also had to route a lot of the bottom PLD traces.. I basically ran out of I/O pins.. Though I did actually have all the databus going to the PLD, when I only actually needed the first eight bits.. So these have been removed to add space for other things..

Primarily, adding a option to boot from the motherboard ROMs. Basically because I want to boot up the machine as normal and then be able to program the flash. Obviously machine isn't going to power up the blank flash ROM. So having the option to boot from the original motherboard ROMs makes it easy to then program the flash memory.

The ATTINY is now wired up. This will act as a storage register for the booster configuration bits as mentioned before. When the machine powers up and in reset still, the tiny will output the registers to the databus where the PLD will then latch the data set various booster settings. This means it is automatically loaded and configured when the machine is powering up.

The register will probably look something like this...

BIT0 (D0) - Flash bank bit 0 (1 of 4 Flash bank select bit 0)
BIT1 (D1) - Flash bank bit 1 (1 of 4 Flash bank select bit 1)
BIT2 (D2) - 32MHz on/off (32MHz or stock 8MHz speeds)
BIT3 (D3) - Int/Ext ROM select (Flash / MB ROM)
BIT4 (D4) - Flash write enable.
BIT5 (D5) - Int/Ext booster on/off select. (use switches or software control)
BIT6 (D6) - Reserved
BIT7 (D7) - Reserved

D8-D13 - un-used / x
D14 - Reserved / x
D15 - Write enable flag for ATTINY

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Re: STE V2 BOOSTER + SRAM STATUS

Post by troed » Fri Nov 24, 2017 7:43 pm

exxos wrote:
Fri Nov 24, 2017 7:24 pm
The ATTINY is now wired up. This will act as a storage register for the booster configuration bits as mentioned before. When the machine powers up and in reset still, the tiny will output the registers to the databus where the PLD will then latch the data set various booster settings. This means it is automatically loaded and configured when the machine is powering up.
Will the ATTINY store in its flash and copy to sram when booting, and then any changes made during regular use & reset will only touch the sram? Reason for asking is that my use for the 8/32MHz register would be to run devpac and compiling in 32MHz and switch to 8MHz when launching the code. Rewriting the flash all the time will quickly wear it out ... :)

(This of course puts additional requirements on the clock cycle change to be made crash-safe which might be too difficult .. ?)

/Troed

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