Help to compile a source file

[Icky]

My finger is now numb from all the power on-off sequences but I have some results from the FPGA MMU DE and LOAD signal timings and they range from the lowest I have seen 64ns to the highest 408ns.

DS1Z_QuickPrint36.png (48.16 KiB) Viewed 3195 times

DS1Z_QuickPrint37.png (48.68 KiB) Viewed 3195 times

DS1Z_QuickPrint38.png (48.58 KiB) Viewed 3195 times

DS1Z_QuickPrint39.png (48.83 KiB) Viewed 3195 times

DS1Z_QuickPrint41.png (48.58 KiB) Viewed 3195 times

[czietz]

So, compared to the original MMU...

a) the delays are too short and
b) they seem to have 16 MHz clock granularity (272 ns - 216 ns ≈ 62.5 ns) instead of a 8 MHz (125 ns) one.
c) Also, in the 68 ns delay shot, the first LOAD pulse is shortened.

Most likely more than one issue remaining with the MMU reimplementation...

[exxos]

I think I understand what's going on with all this now.. I need to tweak the code tomorrow to confirm...

@Icky

[exxos]

The attached scope shots show examples for WS1 (750 ns, 6 cycles) and WS4 (500 ns, 4 cycles).

I'm confused.. if the MMU is allocating 500ns to CPU, then 500ns to VIDEO, then 750ns can't work because the shifter would latch CPU data as its time slot will have gone... the shifter could only get data between 0ns to 500ns for example...

[czietz]

I'm confused.. if the MMU is allocating 500ns to CPU, then 500ns to VIDEO

Um, no. I said that there is a (potential) Shifter cycle every 500 ns. There's also a (potential) CPU cycle every 500 ns. But those two are intertwined; there is a RAM access every 250 ns.

the shifter could only get data between 0ns to 500ns for example...

Remember that the timing between DE getting high and the Shifter cycle where the first LOAD pulse happens is random, either 375 ns, 500 ns, 625 ns or 750 ns (3 - 6 cycles); that's the wake states were talking about.

[exxos]

600ns...

IMG_4905.JPG (101.01 KiB) Viewed 3136 times

IMG_4906.JPG (63.5 KiB) Viewed 3136 times

EDIT:

Been trying various delays, always seems be doing is causing chaos, and I have not yet seen the WS value change to anything different yet.

[exxos]

Still playing around with all this, so far the timings below between DE & LOAD are as below...Values change simply by pressing the reset button..

Code: Select all

424ns WS ?
136ns WS ?
72ns  WS ?
272ns WS2
168ns WS ?

But so far I have been unable to figure out why this timing keeps on changing... I have reset signals on counters and variables state machine and just about everything Including some synchronisation to various clocks, but this value keeps on changing..

I think the glue alters that somewhat as well, as powering on and off it mostly gets stuck between WS1 and WS? instead.