FPGA clock gen ?

[exxos]

Do any FPGA coders here know how to program this up.. I assume it would be simple.

I want to take something like 100MHz clock input and use it to count variables in the FPGA.

If I want to create say 25Khz clock (but many clocks which are not divisible also!) , I would have something like..

Code: Select all

VAR1.CK = 100MHz
VAR1 = VAR1 +1

The calculation would be
100,000,000 \ 25,000 = 4000

So I would have something like

Code: Select all

IF VAR <4000 THEN OUT1 = 0
IF VAR1 >4000 THEN OUT1 = 1
IF VAR1 > 4000 x 2 THEN VAR = 0

So from count 0-4000 the OUT1 will be ZERO.
Over 4000 we flip the bit to 1 and OUT1 becomes 1
If we get to the end of the clock cycle (4000 x 2) then we set it back to zero to restart the count again.

So basically OUT1 will give a clock output of 25,000 Hz (25Khz).

Now if I want a clock 25,050Hz, I just do a new calculation..

100,000,000 \ 25,050 = 3992 clock, and I just use the same code but with 3992 instead of 4000. Then OUT1 will give a 25,050Hz clock output.

I actually want to set this "count to value" from the CPU via a register ultimatly..

[mfro]

Do any FPGA coders here know how to program this up.. I assume it would be simple.

I want to take something like 100MHz clock input and use it to count variables in the FPGA.

If I want to create say 25Khz clock (but many clocks which are not divisible also!) , I would have something like..

Code: Select all

VAR1.CK = 100MHz
VAR1 = VAR1 +1

The calculation would be
100,000,000 \ 25,000 = 4000

FPGA coders know how to do that, but rather don't

Although that will probably work considering your relatively slow target frequencies, usually, you do not mess with the clock but rather clock the target flipflop with the same (main) clock and use calculated enables instead. Most FPGAs have dedicated wiring for the clock network and don't like "calculated" clocks outside (will probably work but likely bring all kinds of oddities).

If you absolutely need a real clock, use the dedicated clock generation circuits (PLL, ...) that are part of every FPGA.

Code: Select all

counter <= counter + 1 when rising_edge(clk) and counter < 3999 else
                 0 when rising_edge(clk) and counter = 3999;
enable <= not enable when rising_edge(clk) and counter = 3999;

process
begin
     wait until rising_edge(clk);
     if enable then
         q <= <whatever logic you need>;
     end if;
end process;

[exxos]

@mfro So what would you suggest for doing the job ?

That was just the only way I could think of doing a clock gen. I do also need 8 separate outputs programmable by a register set by the CPU. They are all unrelated outputs, anything in the audio range really.

[cmorley]

Divide down the main clock with syncronous counters.

Something along these lines.. Verilog pseudocode:

Code: Select all

reg [11:0] half_period; // set elsewhere

reg [12:0] counter;
reg op;
always @(posedge clk)
 	if (counter==0) op<=1'b0;
 	else if (counter==half_period) op <= 1'b1;
 	
 always @(posedge clk)
 	if (counter==(halfperiod<<1) counter <= 0;
 	else counter <= counter + 1;
 

[mfro]

@mfro So what would you suggest for doing the job ?

What I've shown above should do it just fine.