TOS patch for 1.44MB floppy support ?

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Re: TOS patch for 1.44MB floppy support ?

Post by exxos »

The switches goto register FF9200 as far as I can tell. The code agrulund posted shows that. As to why I don't get the format option in gem, no idea yet. It could be checking the switches elsewhere in the code.I'm not sure what the PAL is doing. But not looked much yet. Think it was doing the 1772 clock switching. The PAL doesn't look to have any address lines either.but does seem to hint at address decoded inputs.

When I get home I'll do a proper register fake with flashy-clock and see if it all behaves then.
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Re: TOS patch for 1.44MB floppy support ?

Post by exxos »

Assume the PAL is getting input from FF860E but its not listed in the register map to what it actually is. I assume its related to the 1772 switching clocks. But I don't need that register anyway as I use my own GAL for that stuff.
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Re: TOS patch for 1.44MB floppy support ?

Post by troed »

Well without that register TOS can't switch frequency so TOS 2.06 won't be able to know when to do DD vs HD.
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Re: TOS patch for 1.44MB floppy support ?

Post by troed »

This is the PAL that's needed for HD floppy support (-002 vs early MSTE that came with -001). It's what runs the equations I posted earlier:

Screenshot from 2022-05-25 19-12-51.png
Screenshot from 2022-05-25 19-12-51.png (63.33 KiB) Viewed 1551 times

The outputs then go to another PAL (a 22V10) that does more stuff, but one of the things it does is to output the FCCLK to the WD1772 on pin 15:

Screenshot from 2022-05-25 19-24-53.png
Screenshot from 2022-05-25 19-24-53.png (62.76 KiB) Viewed 1551 times
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Re: TOS patch for 1.44MB floppy support ?

Post by exxos »

I'm not sure what all this has to do with what Im doing though. TOS switches bit 7 in the PSG which goes high or low as it switches clock speeds. TOS itself just tries SD or HD mode until one works. This works fine as a quick hack to enable bit 6 on the dip switches. The gem option for formatting 1.44 is probably elsewhere in the code which I've not hacked, so not concerned about that yet.

Next step is to do a proper register fake for the dip switches and see what happens then.
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Re: TOS patch for 1.44MB floppy support ?

Post by troed »

exxos wrote: Wed May 25, 2022 6:35 pm I'm not sure what all this has to do with what Im doing though.
Alright, maybe I'm misunderstanding :) I thought you wanted TOS 2.06 to be able to do DD and HD just as it does on an Mega STE? No need for any HD sense input from the drive (the way regular HD hacks work on STs). For TOS 2.06 to be able to do this the PAL is critical, and it decodes an address TOS uses to switch frequency to the WD1772.
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Re: TOS patch for 1.44MB floppy support ?

Post by exxos »

troed wrote: Wed May 25, 2022 7:54 pm I thought you wanted TOS 2.06 to be able to do DD and HD just as it does on an Mega STE? No need for any HD sense input from the drive (the way regular HD hacks work on STs). For TOS 2.06 to be able to do this the PAL is critical, and it decodes an address TOS uses to switch frequency to the WD1772.
Ah.. I see the confusion, as there are basically 3 ways of going about this and they are getting mixed up a bit. I am currently using the TOS patch for "auto detect" SD/HD like the MSTE does (as in auto detect SD/HD, not the method used to get there via hardware) . Mine uses the PSG to select SD/HD on my Floppy GAL on the H5. So I don't need the other PAL chips etc, This seems to work well. I posted the image of the "bodge wire" here https://www.exxosforum.co.uk/forum/viewt ... 575#p85575

I thought the MSTE registers would do the same to fool TOS into doing the same (as the MSTE would) , but like you mention, its using a bunch of other PAL's to basically do what my floppy controller GAL does anyway in switching the 1772 clock. It just needs TOS to tell it which mode to use, which seems nested in a bunch of other stuff :roll: There doesn't seem to be a simple way to just enable 1.44 support in TOS206 :( Its kinda annoying as TOS itself can read HD floppies, its just the "auto sense switching" which is the problem. I thought there may be some PRG to enable it or something but seems not. Which is why I started this thread for a simple PRG to sort it out.

The other register looks like this it seems

Code: Select all

/* bits 0 and 1 of $ff860e */
/* 0x00 : FDC operates in DD mode */
/* 0x03 : FDC operates in HD mode */
Assuming that's what the GAL is taking care of. But its irrelevant if I can't even get that far without fooling TOS into thinking its a STE or something. In anycase, it's going down a over complicated rabbit hole of chaos that way.

Anyway, Will just have to build a patched 206 as I am using now. It only needs a wire from the PSG to the floppy SD/HD pin on my GAL. Annoying as I already have a TF536 build of TOS206, now there will be another variation to enable the auto SD/HD switching :roll: I assume EMUTOS won't like this method either :shrug:
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Re: TOS patch for 1.44MB floppy support ?

Post by exxos »

Also explains this old mystery in FCOPY as well (PSG bit 7) . But don't see what TOS would do this "out of the box" ..unless FCOPY takes care of it.

Steem__00001.png
Steem__00001.png (13.15 KiB) Viewed 1515 times

Also don't follow what TOS does when a floppy isn't formatted. How does it know if its got a SD / HD in ?!

Been trying to find what mods used the PSG bit 7 but can't find anything at all in my searches :(
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Re: TOS patch for 1.44MB floppy support ?

Post by atari030 »

Pardon my ignorance, but how does TOS 3 and 4 differ? I've never opened my TT but doesn't the Falcon have solder pads that relate to Ajax floppy support?
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Re: TOS patch for 1.44MB floppy support ?

Post by troed »

exxos wrote: Wed May 25, 2022 10:46 pm Also explains this old mystery in FCOPY as well (PSG bit 7) . But don't see what TOS would do this "out of the box" ..unless FCOPY takes care of it.
Maybe a KAOS TOS thing - or someone actually made a PRG back then? I've never seen that before. Also it does say "input" for some reason.

I was thinking though. If you have some CPLD free to do an additional address decoding you could make it work without TOS patching - just emulating so that when TOS addresses the "PAL" your CPLD output triggers the PSG bit 7.

While I thought UA2 (the PAL -002/-001 version) did most of the work, it's clear the 22V10 is equally important in the Mega STE to make this work. The PAL only does the address decoding - actually looking at the data bus (bits 0 and 1) is done by the 22V10. I guess that's why the PAL20V8 equations don't make a lot of sense by themselves.
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