V2.6 under design (supersedes the V2 .2) - project now abandoned

Help & information about the V2.2 booster.
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Re: V2.6 under design.

Post by exxos » Tue Dec 05, 2017 4:38 pm

Okay so I basically, almost, figured this out.. It is actually the same problem I had with my larger V2 PLD booster design .

a1.png
a1.png (138 KiB) Viewed 662 times
The image on the left is the 8 MHz clock is generated from the MMU. This does not work..

The image on the right, the same signal, but with a 1K pull-up resistor to 5 V... This does work.. And I even tried it on 2 of my booster boards which failed to work previously, and now both work with this mod..

I wasn't expecting to have this problem with this design, only with the larger newer Atmel PLD's. But this problem has shown its ugly head with this new V2 design :roll: and the PLD uses totally irrelevant..

I am still not really sure what is going on.. Either the undershoot is causing some internal latch up the CPU.. Or because of grounding issues all over the motherboard, it is possible the undershoot may be seen as 0 V, and then the low voltage is actually 1 V all the time, which means the CPU never sees a logic low.

What I saw before was really bad ringing could be seen as logic pulses which are not supposed to be there. When this was clamped, the problem went away. This does not seem to be anywhere near as bad the current PCB design, only a tiny bit of difference is there but it seems enough to cause chaos.

Though it is likely that while this works with a normal TTL based 68000, it is probably loading the 8 MHz line enough to keep it stable across the motherboard. Then when I place CMOS 68000, the load on the 8 MHz line is a lot less, and it could be causing ringing somewhere else further down the line on the motherboard. Which upset something else, maybe the glue...

So all future booster designs will need to have some sort of loading on the 8 MHz clock signal to keep it all stable. A very annoying problem which really needs a lot more investigation, but I'm not going to spend any more time investigating this matter.

EDIT:

Annoyingly, its started to act up again on both boards. :cussing: I think the STFM is just a bad machine from start to end. I never have any issues hardly with the STE :roll:
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Re: V2.6 under design.

Post by exxos » Tue Dec 05, 2017 9:50 pm

Still puzzling over this.. I have a TTL CPU, and just the basic board as a adapter again. It only seems to work when I press down firmly in the centre of the board above the dip socket..

I have resold this board many times..
I have also re-solder the motherboard couple of times.
The motherboard works fine with my original V2 booster, and a original CPU .
I have added some socket pins onto the booster in case there was actually a bad connection, still same behaviour.
I think I have ruled out socket, I have literally been melting it with the CPU in place to get rid of the plastic spacers. This did not really change anything..

So I am basically back to thinking the PCB itself is somehow faulty. I have continuity checked it twice, and it all seems to check out. But maybe when it is inserted into the motherboard bends the board slightly somehow and breaks the connection somewhere. But I have also checked all the CPU signals both ends, and they all seem to be active and working anyway..

Only thing I can do is get these boards made again by OSH, and hope that it is a faulty loaded PCBs I got "on the cheap". Even though actually there weren't exactly that cheap...

Or try and redo the original booster design ROM six layers into four layers. Which is basically what I did with this new design anyway. I guess I could just get both boards made.. Though it is getting over £100 a go :roll: rerouting the entire board again isn't going to be fun either, and this does not mean something else isn't going to go wrong with a new PCB layout :roll:

EDIT:
Ordered the current V2.6 board from OSH. No super quick option on checkout :( But paid for UPS as postage takes a while USPS.. Hopefully they will come before xmas so I can try those boards instead...
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Re: V2.6 under design.

Post by exxos » Mon Dec 18, 2017 9:15 pm

New PCBs came today..

Quickly assembled one up just to test it as a stock system..

IMG_2126.JPG
IMG_2126.JPG (135.54 KiB) Viewed 610 times

It booted up right away, and has currently been running for about an hour.. So it is clear cheap PCBs for 4 layers really is not a good idea :roll:

I will try and find some time this week to try the booster logic on this board..
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Re: V2.6 under design.

Post by rpineau » Tue Dec 19, 2017 3:16 am

Which PCB vendor did you use for the "non working" one.
I have fairly good result with PCBWAY recently.
Of course OSHPark is good but from time to time I get some issues with them
Dirtypcbs seems ok for 2 layers, not sure of their capability for 4 layers.. I have some 4 layers from them that I haven't tested yet (68040 -> 68060 adapter).

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Re: V2.6 under design.

Post by exxos » Tue Dec 19, 2017 11:41 am

rpineau wrote:
Tue Dec 19, 2017 3:16 am
Which PCB vendor did you use for the "non working" one.
I have fairly good result with PCBWAY recently.
Of course OSHPark is good but from time to time I get some issues with them
Dirtypcbs seems ok for 2 layers, not sure of their capability for 4 layers.. I have some 4 layers from them that I haven't tested yet (68040 -> 68060 adapter).
I use Sitopway. They are really cheap for PCBs, I have used them a lot in the past, but quality is always very low. I thought it may be okay for these prototypes, but obviously not.

Problem with is substandard FR4 quality. The copper comes off really easy from the PCB. So small pads like on TQFN type packages, if you tried to correct a solder short, then the pad would always come off as well and the board would be ruined. I think poor quality with poor quality buyers just means that slight bend in the circuit board, or little bit too much heat on the pad, and it breaks the vias internally probably on internal traces.

I did my first order to dirtypcb a couple of weeks ago, this was just a simple two layer board, the released I can investigate the quality of their boards. But mostly my boards are too large for the 5x5cm service, and their price seriously jumps up high after that, in particular with four layer boards.
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Re: V2.6 under design.

Post by rpineau » Tue Dec 19, 2017 4:00 pm

You should take a look at pcbway.com
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Re: V2.6 under design.

Post by exxos » Tue Dec 19, 2017 4:18 pm

I turned on this machine this afternoon and basically would not boot up.. This sounds very much like the original problem I had, but this problem seems different with these PCBs compared to the other ones.. Sometimes machine does actually boot even start to do memory test but then just locks up for no reason at all.

The thing I have found odd is with the original CPU I see this on A5.. (And indeed other signals as well)

db1.png
db1.png (4.08 KiB) Viewed 586 times

Which seems basically fine..


However with my new board I see this..

db2.png
db2.png (3.95 KiB) Viewed 586 times
There is no power supply rail issues on this board and there are no other issues anywhere that I can see. But I seem these 1volt pulses are the reason why the board does not work.

This is basically just a DIP to PLCC adapter still using a TTL CPU.. So there should be no real difference between the two other than the PCB itself.

Even more odd is that those pulses are at exactly 2 MHz. The only 2 MHz signal is generated by the MMU and this is not even used on my board. However if this was some sort of interference, it should not be apparent on every signal on the bus.

I tried adding pulldown resistors to the address and databus, these spikes are indeed a lot less, but machine still refuses to boot :(

At this point I have absolutely no idea why these noise spikes happen with this particular booster PCB. Not really sure if the PCB itself is the problem or not. I could understand some extra noise due to the extra PCB track length to the CPU, but not consistently at 2 MHz signal. I even tried totally different motherboard revision and still have the same issues.

I can only really assume that my original V2.2 design works because it is on six layers. Whereas each signal is sandwiched between GND layers. This will add somewhere around 20pF capacitance to each signal which could be enough to act as a snubber to flatten out these 2 MHz pulses. Looking at the same signals on my the 2.2 booster those noise spikes are practically nothing.

Even more odd is the other booster noise working on which is similar but more aimed towards 32 MHz speeds, using the larger ATMEL PLD is created on four layers to work reasonably well. Though in this case I have rooted a lot of address and data lines to the PLD which could be actually helping of the noise on the lines enough so that it actually works.

So at this point I'm just going to assume my the 2.2 booster works because it is basically clamping down on these noise spikes which I had no idea was there until today. I could go back to the 2.2 booster design and produce them again, but I really do not want to use six layers as it is incredibly expensive and I have to get a lot of them made to keep the costs even somewhere sensible. Which was the whole reason I was trying to do the board with four layers.

EDIT:

I tried adding 50pF capacitance onto one of the address lines, and it did not seem to make any difference to the noise spikes :( So at this point I'm just totally perplexed by this.

The only real solution will be to buffer the entire CPU lines, which really would not be fun and I'm getting a little tired of doing booster PCBs over and over as they are so time consuming to design.

The only real guess I can come up with is that because this 4 layer PCB is a lot more compact with the tracks, that all the signals are creating interference with all the other signals and somehow adding up to the constant 2 MHz pulses which I see.. Of course this then means that any potential booster design I do could end up with the same problem.. And of course keep creating PCBs is adding up to a huge cost, and not only the time involved as well.

I will give it a little bit more thought over the next days, but I think it may just be wise to abandon the STFM boosters altogether and concentrate on the STE. I never had any problems with the STE with any of my projects. The STFM has just been a total nightmare since day one..So if anyone has any suggestions on where these 2 MHz waves are coming from then I can look into it..
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Re: V2.6 under design.

Post by exxos » Tue Dec 19, 2017 7:07 pm

I have been investigating the capacitance on the signals some more...

11111111.png
11111111.png (3.71 KiB) Viewed 571 times
The above image is when machine fails to boot. The 2 MHz spikes jump up to around 800mV. I'm just going to assume here that this is being seen as a logic high.. Even though technically we need 2 volts... So it's a WIP theory..

22222222.png
22222222.png (3.68 KiB) Viewed 571 times
The above image I added 390pF onto the signal and it reduced spikes to around 300-400mV. I checked on my the 2.2 booster and that was about the same voltage level as I saw there.. So that voltage range should be fine..

(EDIT: I think I had the pull-up resistors twice requiring such a high capacitance to make the difference)

So I investigated the capacitance on the PCBs itself..

new.jpg
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The new booster board has approximately 8pF capacitance between 0 V and 5 V..


old.jpg
old.jpg (82 KiB) Viewed 571 times
The original the 2.2 booster has about 50pF between 0 V and 5 V...

Am not really sure of the interaction of having a signal with 50 PF to 5 V and 50 PF to 0 V.. I'm going to assume this is the equivalent of 100pF load on the signal..

So I retested capacitor on A5 more carefully with 50pF..

I see approximately 840mV with no capacitor, 640mV with 50pF.. And I'm going to assume 440mV with 100pF.. So we are right on the ballpark figures now..

So I think it is safe to say at this point, this capacitance is the reason the 2.2 booster works, and this new booster does not... The mystery of where the 2 MHz pulses are coming from still a mystery... And is going to assume at this point there is some funky internal switching going on the HC CPU causing these spikes..

EDIT:

I found some 100pF capacitors and connected them all to the address and databus. With the TTL CPU it did actually tried to boot and showed the RAM amount before it crashed. I rebooted several times and it always got the same point. I swapped for another booster board I made a couple of days ago and this did not work but I could not measure the noise either to boot. So I plugged in the board with the capacitors without this board does not boot again either... Motherboard however works perfectly with the normal CPU still..

I have half wonder about using resistors in series the address and databus lines not the noise that way.. But not very fun to do..
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Re: V2.6 under design.

Post by exxos » Thu Dec 21, 2017 10:40 am

So my test machine was turned off all of yesterday and I turned it on this morning and it booted right up. Where they crashed after a few seconds in memory test. Rebooting the machine went as before a right effort.. Basically a lot of the time just garbage on the screen.

As a start I put the booster board in about 10 CPU sockets to lift it away from the motherboard to rule out interference.. This did not change anything..

I started to scope out the noise pulses in relation to other signals on the motherboard such as the main clocks.

bb.png
bb.png (4.59 KiB) Viewed 546 times
What we have here is the 4 MHz clock with address line 5. It looks like there is some relation there but there actually isn't. To save a bit of forum space, the 2 MHz clock was more in sync with the noise pulses but, the pulses were in the middle of the low part of the 2 MHz cycle. So it can be ruled out I think that this is any sort of 2 MHz related switching noise.

I also tried adding 100R in series with address line 5 scoped either side to see if I could work out where the noise was being generated, but I did not see much difference. I did a lot more testing, but I won't publish it here, as it was nothing much relevant..

What I did find was this between address line 5 and address line 6..

capa5a6.png
capa5a6.png (4.25 KiB) Viewed 546 times

This looked like a clue.. Basically thinking each address line is causing crosstalk onto other address lines as this is what the image looks like..

I measured the capacitance on my new booster board between those signals and read about 7pF. I also checked my original the 2.2 booster board, and measured 13pF there. As I have a lot of parallel traces on my new booster board, I decided rather than struggling trying to test every combination of track, I would assume 25pF as a reasonable value, so I just soldered a capacitor across address 5and 6 to see if I can cause more interference.. Long story short, I did not see any difference whatsoever.

I am not ruling out PCB capacitive coupling totally, as with so many address line switching would be generating a lot of interference with I cannot easily simulate.. And this point I am not ruling it out, but at the moment it seems unlikely to be the issue.. Most of the parallel traces are actually on the databus, which does not seem to suffer so much with this problem some reason, but I would need to look into it some more to confirm..

It would seem more like power rail noise, for example, all the address line switching up and down would cause ground bounce on the CPU, which I have seen before, and can easily spike 1 V. However I have done a lot of testing with ground points and power rails and do not see anything problematic there.

These pulses seem to be a lot more than just simply interference, as if it was simple interference between signals then it would not really take much to change the amplitude of them, such as adding the 25pF capacitance there.

One odd thing I have spotted is that the noise pulses do not seem to be there initially when the machine turns on. My TOS104 version is patched by
Peter show the TOS version and RAM size on power or where it delays for about 10 seconds before continuing to the desktop.. I need to investigate some more, while it is at that point and the address bus still switching, the noise pulses do not appear to be there.. As soon as ram test starts the noise is always there.

I did wonder if the noise is generated when the CPU is accessing the ROM for example. In part this was what I saw on the STE and actually let me to the new DMA investigations... In any case, I have not yet found a relation between accessing the ROM or not.

I also tried looking at the RAM isolation buffers, looking at the relationship between the noise and the MMU control signals to the latches.. I did not see anything there either..

My first guess, is that when the CPU is accessing some chip on the motherboard, interference starts on the bus somewhere. Again this is what I saw on the STE. But so far on the STFM I have not found a likely cause for this yet.

But there is still another problem, that when the original DIP CPU is in place, I do not see this noise. I have ordered a DIP HC CPU which I will just try in the motherboard to see if the noise problems get worse or not. The HC CPU should be easier to drive than the TTL, so in theory at least, any noise on the motherboard should be visible on the HC CPU A lot more.

I have designed a six layer version of this board and used the auto router, but the cheapest I can find get this manufactured is £150. Which I really do not want to spend for a third time this project..

So I will just have to see what happens with the HC CPU... If I do not see any noise there, noise has to be generated somehow on this new booster board.. But as to why this is, I really do not know..
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Re: V2.6 under design.

Post by exxos » Mon Dec 25, 2017 9:56 pm

Only home for a short while tonight, but did a very quick test between the TTL DIP & CMOS DIP CPU...
tc.png
tc.png (7.72 KiB) Viewed 498 times
The CMOS is a fraction more noise, but not by a great deal...

I tried adding a 1 foot length of wire into address five, noise did increase a fraction, but nothing really significant. I also tried adding 25pF onto the wire and did not really make any difference.

I had a thought that I should just look at the relation with address strobe..
t4.png
t4.png (4.32 KiB) Viewed 496 times
So basically here, I added a 2k2 pull-up on the signal as well, and it doubled in amplitude. Should not make any difference at all as it is CPU likely trying to go tri-state during each bus access.

So I think I cannot really say now that this is a noise -related issue :roll:

I tried the booster board again just, with the TTL CPU, and is currently behaving.. But this again is what was happening before.. It seems I when something warms up, something starts screwing up really badly causing the machine not to even tried to boot..

I also just tried the CMOS CPU, and just get a white screen where the machine does not try to boot at all.. Again this sounds like the issues I had with the CPU sockets.. But as far as I can tell the connections look fine.. And I do not see any difference between CPU and motherboard signals. So in this case it would rule out the socket.. However it has to be something amiss somewhere..

At this point the only thing I can do is create a new CPU adapter PCB.. Similar like the STE booster design, where I solder the CPU to the PCB, and then the pins push into the socket.. Though really this test might still not be fair as if there is a fracture on the actual CPU pin somewhere, after soldering, and still using the socket could be a bad idea..

So only thing I can do is literally create a clone of this booster board, but using the CPU which is soldered onto the board instead of using a socket :roll:
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