Re: V2.6 under design.
Posted: Tue Dec 05, 2017 4:38 pm
Okay so I basically, almost, figured this out.. It is actually the same problem I had with my larger V2 PLD booster design .
The image on the left is the 8 MHz clock is generated from the MMU. This does not work..
The image on the right, the same signal, but with a 1K pull-up resistor to 5 V... This does work.. And I even tried it on 2 of my booster boards which failed to work previously, and now both work with this mod..
I wasn't expecting to have this problem with this design, only with the larger newer Atmel PLD's. But this problem has shown its ugly head with this new V2 design and the PLD uses totally irrelevant..
I am still not really sure what is going on.. Either the undershoot is causing some internal latch up the CPU.. Or because of grounding issues all over the motherboard, it is possible the undershoot may be seen as 0 V, and then the low voltage is actually 1 V all the time, which means the CPU never sees a logic low.
What I saw before was really bad ringing could be seen as logic pulses which are not supposed to be there. When this was clamped, the problem went away. This does not seem to be anywhere near as bad the current PCB design, only a tiny bit of difference is there but it seems enough to cause chaos.
Though it is likely that while this works with a normal TTL based 68000, it is probably loading the 8 MHz line enough to keep it stable across the motherboard. Then when I place CMOS 68000, the load on the 8 MHz line is a lot less, and it could be causing ringing somewhere else further down the line on the motherboard. Which upset something else, maybe the glue...
So all future booster designs will need to have some sort of loading on the 8 MHz clock signal to keep it all stable. A very annoying problem which really needs a lot more investigation, but I'm not going to spend any more time investigating this matter.
EDIT:
Annoyingly, its started to act up again on both boards. I think the STFM is just a bad machine from start to end. I never have any issues hardly with the STE
The image on the left is the 8 MHz clock is generated from the MMU. This does not work..
The image on the right, the same signal, but with a 1K pull-up resistor to 5 V... This does work.. And I even tried it on 2 of my booster boards which failed to work previously, and now both work with this mod..
I wasn't expecting to have this problem with this design, only with the larger newer Atmel PLD's. But this problem has shown its ugly head with this new V2 design and the PLD uses totally irrelevant..
I am still not really sure what is going on.. Either the undershoot is causing some internal latch up the CPU.. Or because of grounding issues all over the motherboard, it is possible the undershoot may be seen as 0 V, and then the low voltage is actually 1 V all the time, which means the CPU never sees a logic low.
What I saw before was really bad ringing could be seen as logic pulses which are not supposed to be there. When this was clamped, the problem went away. This does not seem to be anywhere near as bad the current PCB design, only a tiny bit of difference is there but it seems enough to cause chaos.
Though it is likely that while this works with a normal TTL based 68000, it is probably loading the 8 MHz line enough to keep it stable across the motherboard. Then when I place CMOS 68000, the load on the 8 MHz line is a lot less, and it could be causing ringing somewhere else further down the line on the motherboard. Which upset something else, maybe the glue...
So all future booster designs will need to have some sort of loading on the 8 MHz clock signal to keep it all stable. A very annoying problem which really needs a lot more investigation, but I'm not going to spend any more time investigating this matter.
EDIT:
Annoyingly, its started to act up again on both boards. I think the STFM is just a bad machine from start to end. I never have any issues hardly with the STE