CURRENT PROTOTYPE STATUS (SEC 64MHz 68000)

[IngoQ]

Whoa.... Was there ever before a 68000 running at 50MHz in a computer?

Congrats!

[exxos]

Whoa.... Was there ever before a 68000 running at 50MHz in a computer?

There are those "miming" things which use the SEC at 50MHz.. but AFAIK there has never been a 50MHz 68000 in Atari... IIRC the T28 could be fastest.. but think they did a T36 or something as well...

I have been thinking about the now "slow" ROM.. Thinking along the lines of copying the ROM to SRAM before the 68000 starts... So ROM will be held in SRAM at normal TOS104 space.. I think the CT60 does something like that.. but not sure if it changes address or not... But should be possible to do direct copy from ROM to SRAM very quick, then machine boots TOS from SRAM...

[stephen_usher]

That's crazy. Well done! In terms of integer division, how would a 50mhz 68000 compare to TT's 32mhz 030?

Well 030 has a cache so will be faster for the same clock speed, plus 030 is more efficient core.. you would have to benchmark it with GB6 and see what it outputs with and without caches enabled.. Which would be useful anyway as we don't have a TT benchmark vs stock ST.. or Falcon in fact..

Well, here's the GEMBench output from a TT...

[exxos]

Well, here's the GEMBench output from a TT...

cool! What do you get without caches ?

[exxos]

Only just got home.. but quickly tried 60MHz with my RSO.. it tries to boot, but not really get far enough to boot from floppy (it did half boot GB6 once).. I did some code changes and it not helped.

64MHz doesn't even try to boot as tried yesterday.. So likely max speed of CPU is around 55MHz... Likely why designs I see mostly use 50MHz.

I will see if there any options for OSC around 55MHz... will also try the speed tomorrow..

[stephen_usher]

OK, I did three more tests for sort of completeness...

ST Medium resolution, no caches


TT Medium resolution, with cache


TT Medium resolution, with cache, program in TT-RAM

[exxos]

OK, I did three more tests for sort of completeness...

Thanks! just goes to show the 030 is like 50% faster at int-div! (i've posted the images in the benchmark section as well).

[Atarian Computing]

Thanks for the benches. Wow, so I was expecting a bigger difference. So this mofo will be a scorching fast booster!

[exxos]

Thanks for the benches. Wow, so I was expecting a bigger difference. So this mofo will be a scorching fast booster!

If ran from fast-ram yes... The STE can beat most scores at 32MHz, but can't speed up ST-RAM.. TT shows almost 250% there.

[exxos]

After looking at some scope images of E-clock it hardly ever goes high now and I think I can just emulate it a lot easier than the normal methods of emulating E-clock..

So my investigation showed that when VPA goes low, about 200ns later VMA goes low.. But then there is a huge delay of 1,000NS before the ACIA CS goes high (high is enabled). It seems GLUE is using the E-CLOCK to trigger the ACIA CS line..

So what I did was remove all the delays and E-CLOCK totally and just did this..

Code: Select all

VMA.CK = CLK8;
VMA.D = VPA;
!E = VMA;

CPU_DTACK = 'b'0;
CPU_DTACK.OE = !ST_DTACK
               # !VMA;
               
!AVEC =  FC2 & FC1 & FC0 & A19 & A18 & A17 & A16 & !VPA ;

So basically everything happens at the same time. !E will be asserted for one 8MHz clock cycle is approximately 125ns. The 6850 datasheet says the minimum HI time is 210ns... But we know we can double clocked these anyway so 100ns.. So it basically tallies up and seems to work fine.

This is of course running a stock 8MHz system just to prove works...

Though if I transfer these changes over to the 50MHz code, then in theory still works just the same... So I need to try