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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS

Posted: Sat Jul 21, 2018 4:36 pm
by Atarian Computing
exxos wrote: Wed Jun 06, 2018 10:37 pm TOS206 is needed for alt-ram, not a problem for the booster. I have no idea what use alt-ram is, but people keep nagging about it, people buy monster for alt-ram and IDE, so its half step there for now.
I would give anything to be able to run Sparemint on my STacy. That needs a lot of alt-ram.

Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS

Posted: Sat Jul 21, 2018 6:38 pm
by exxos
Atarian Computing wrote: Sat Jul 21, 2018 4:36 pm I would give anything to be able to run Sparemint on my STacy. That needs a lot of alt-ram.
It will have alt-ram at least next design, likely flash and fast-rom.. though flash software will be something someone else may have to code else I will be spending months on it myself otherwise.

Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS

Posted: Sat Jul 28, 2018 1:17 am
by robdaemon
This would be a great upgrade for my Mega ST2. I have a Marpet 8 MB board for it, but it's not usable without TOS 2.06.

Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Posted: Mon Nov 12, 2018 10:03 pm
by exxos
No updates to report yet :(

But now I have had but experiences with the level translators, and is going to continue this design with 5V stuff. You will take a fair while just to get the regular ROM connected up and working. But if doing the new board, I would want to put fast ram on there as well..

Though back to the point that the SRAM is about £10 per MB. This will give up to 50MHz fast-ram speeds. There are of course the maximum would generally be 8MB (£80) though I have suggested 10MB or 12MB before, but I think there was some problem with possible conflict with external graphics RAM or something..

So I will probably add on space for 8 chips for now.. Then they can be populated in 1MB steps. Likely I would only fit 1MB for testing purposes anyway. Cheaper to kill 1 chip than 8 :)

Really I just want to discontinue the V2.2 booster, and get this current design and running as it is the V2.2's successor. Of course I want to not just ramp up the speed, but add the new to it like the long-awaited fast ram. I have of course considered adding flash ROM, and and even IDE, but each new feature could take several months to test and debug individually. The trying to bring up everything on one card at once, is not really realistic to do.

Of course this project has been on hold for some months again, but I hope in the New Year I can spend bit more time on this again. Of course wiring up ROM & RAM really only comes down to PCB routing time. There is the firmware as well, but that should really be pretty simple to do as well.

Incidentally I do actually have 2 of the SEC prototypes somewhere which if anyone wants to purchase one, I will try and find them flash the firmware into them.. It is just the 50MHz CPU running... Benchmarks here... https://www.exxosforum.co.uk/forum/viewt ... =160#p6266 Not terribly exciting to say the least...

Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Posted: Mon Nov 12, 2018 10:18 pm
by PaulJ
Exxos does it have the decode TOS 2.06 does it run reliably..?

Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Posted: Mon Nov 12, 2018 10:21 pm
by exxos
PaulJ wrote: Mon Nov 12, 2018 10:18 pm Exxos does it have the decode TOS 2.06 does it run reliably..?
You mean the current SEC booster ? There is no ROM yet.. that comes next...

The current boards look like this...

https://www.exxosforum.co.uk/forum/viewt ... =110#p5938

Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Posted: Tue Nov 13, 2018 11:29 pm
by exxos
Small progress...

Schematic updated, removed the flash (was 3.3v stuff!) and added the fast-ram. Seems I probably only need 4 chips for 8 MB...

Added in the normal PLCC44 ROM...

This is all I am doing with this booster.. but that is enough to keep me busy for some time yet...

sec2f.png
sec2f.png (536.55 KiB) Viewed 4549 times

sec2.png
sec2.png (242.2 KiB) Viewed 4549 times

Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Posted: Tue Nov 13, 2018 11:42 pm
by rpineau
I don't see the SRAM[1..4] signals on the CPLD

Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Posted: Tue Nov 13, 2018 11:47 pm
by exxos
rpineau wrote: Tue Nov 13, 2018 11:42 pm I don't see the SRAM[1..4] signals on the CPLD
Well spotted!

I need to work out what is the best pins for routing them to the PLD yet though.. There is no ROM_OE pin yet either.

Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Posted: Tue Nov 13, 2018 11:51 pm
by rpineau
You have ROM_OE on pin 29 :)