V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by exxos » Tue Jan 08, 2019 11:58 am

So with a fresh tired mind today, I got one of the other SEC boards working..

So the point it is at, is GLUE does ROM decoding, in parallel with the PLD. The PLD actually drives ROM_EN. GLUE still issues DTACK to the CPU. So this all acts like a stock 8MHz machine basically. TOS104 works fine that way.

So adding in DTACK to drive TOS206, it doesn't even try to boot up. So when GLUE is taken out of the mix (it won't decode TOS206 address) it goes a bit nuts.

I'm also remembering on my STE booster I HAD to drive the CPU into 8MHz on BR,BG,BGACK for it to work reliable. In which case what would likely happen is during a ROM access, the CPU would get slowed down to 8MHz because it will see BR going low.

So I guess the equivalent logic to this, is when I issue DTACK to the CPU on ROM access, if any of the bus grant lines are low (basically BR) then I need to wait 3x CLK8 cycles before I let the CPU see DTACK for that ROM access. Doesn't make much sense, but will try it.

I guess the likely issue is GLUE for some reason expects to see EXACTLY the proper timings for bus grant stuff. Even so I have added in various delays to emulate that, and any delays seem to make things worse :roll:

EDIT:

Thinking about it a bit more, the bus grant stuff shouldn't matter anyway as the CPU will run as a 68000 does at 8MHz, So shouldn't be any reason why TOS206 doesn't boot.
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by exxos » Tue Jan 08, 2019 1:40 pm

So I have now working TOS104 & TOS206 at 8MHz. So it seems, even if I disable GLUE during TOS206 access (which GLUE doesn't decode anyway) it refuses to boot up.. So the plot thickens... I'm going to assume GLUE thinks it can start a BR as nothing is using the bus because it never sees /AS going low.

EDIT:

So it seems that idea is on the right track... What I do now is...

ST_BG = CPU_BG # !CPU_AS ;

I actually do that in the V2.X series of booster as well :roll:

So GLUE seems to think it can do something, when it can't, basically because its not seeing /AS go low anymore.. and I have to disable GLUE and stop it from decoding ROM as its DTACK control is terrible and not fast enough for fast-rom.

So the work-around, is to simply wait for the CPU to finish with the bus, then send BusGrant to the GLUE...

So next up I need to go back to the 50MHz osc and start working on those changes again :roll:
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by PhilC » Tue Jan 08, 2019 3:00 pm

:dualthumbup: Well done.
If it ain't broke, test it to Destruction.

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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by exxos » Tue Jan 08, 2019 4:47 pm

So far not having much luck with 50MHz. The same issues as before that TOS206 won't decode and only TOS104 work. Formatting a floppy brings the error box up initially as before. I've tried like 500 versions of timings and variations of stuff and there isn't anything really else *to* change.

I think its just a inherent problem in the GLUE that because it doesn't see /AS going low, it starts to do something else which causes the problem.

The only way to get the format to behave, is with 3xCLK8 delays on ROM DTACK... So no fast-rom access there. But TOS206 still doesn't decode.. can only assume even though GLUE sees AS going low, its still not behaving and starting to do something which it shouldn't. I thought delaying BG to the ST by 3 or 4 clocks would emulate that timing, but doesn't seem to make any odds :(

So I have no other things to try really with this now :( I have pretty much exhausted everything I can try. The only possible option is to run the CPU in 8MHz when doing bus grant stuff, or any bus access.. but I can't do that on this current board and would need to do a new board :roll: There isn't really any guarantees that even doing that would work.

I have been looking at the PAK020 code to see how that does stuff... The only thing I can spot really is they isolate LDS, UDS when I don't. Though I never had any issues with that before.
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by rpineau » Tue Jan 08, 2019 7:22 pm

On the 68020 card we do have to deal with this and we need to take the BR/BG/BGACK from the ST as well as the ST_AS and CPU_AS to make sure we let the system know when the bus is used by the CPU (68020) and thus assert ST_AS to prevent the glue/GSTMCU from trying to take the bus as there is a bus cycle in progress.
this is a sample from our VHDL code :

Code: Select all

strobes_sync: process (RESET, BGACK_ST, AS_CPU, DS, CLK_SYS, st_access) -- sync AS, UDS, LDS to system clock
	begin
		if BGACK_ST = '0' then		-- blitter is bus master
			AS_ST <= 'Z';
			LDS <= 'Z';
			UDS <= 'Z';
			RW_ST <= 'Z';
		elsif RESET = '0' or AS_CPU = '1' or DS = '1' or st_access = '1'  then
			AS_ST <= '1';
			LDS <= '1';
			UDS <= '1';
			RW_ST <= '1';
		elsif rising_edge (CLK_SYS) then
			AS_ST <= '0';
			LDS <= not SIZ1 and SIZ0 and not A0 and not RW;
			UDS <= A0 and not RW;
			RW_ST <= RW;
		end if;
	end process;
st_access is a signal that is to see if we're using 16bit bus or 32 bit bus (TOS is 32 bit i our case).

Code: Select all

	-- st_access prevent the St from seeing 32 bit address space access as shadow access
	st_access <= '1' when	(tos_rom_cs = '0')
						or (intr_ctrl_addr = '0')
						or ( Address_bus >= x"01000000" and Address_bus < x"80000000")
						or ( Address_bus >= x"90000000" and Address_bus < x"FE000000")
						else '0';
and our TOS chip select :

Code: Select all

	tos_rom_cs <= '0'	when	(Address_bus >= x"0" 			and Address_bus < x"8")
								or (Address_bus >= x"00E00000" 	and Address_bus < x"00F00000")
								or (Address_bus >= x"FFE00000" 	and Address_bus < x"FFF00000")
				else '1';
As the SEC is wired for 2 wire bus master management there are a few things that differs but the important part is to let the GLUE know a cycle is in progress
Working ones : MegaSTE (68020) / TT030 / Falcon with AB040 & Eclipse / 1040STF
Need testing : Falcon with CT2

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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by exxos » Tue Jan 08, 2019 7:47 pm

rpineau wrote:
Tue Jan 08, 2019 7:22 pm
As the SEC is wired for 2 wire bus master management there are a few things that differs but the important part is to let the GLUE know a cycle is in progress
Yep works fine in 8MHz...

OK so I don't do anything with LDS, UDS, but Also I just saw RW in your code...
Why do I just have a feeling that is likely a problem here as I never thought about tristating RW as never need to on the V2.x series, but that isn't running at 50MHz :cry: :cry: :cry:
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by exxos » Tue Jan 08, 2019 9:44 pm

Got side tracked here fixing the SEC footprint viewtopic.php?f=35&t=1534&p=16701

Now the job of tidying up my board again... Then will see how I can route RW,UDS,LDS via my PLD...
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by BlankVector » Tue Jan 08, 2019 9:57 pm

exxos wrote:
Fri Jan 04, 2019 10:22 pm
I have asked EMUTOS guys if they have any clues about it...
Hey, I'm back to business!
As I understand, you have that format error with accelerated CPU and ROM, right?
You have the very same error with both TOS and EmuTOS. That's really strange because the BIOS is completely different. EmuTOS's BIOS has been rewritten from scratch. On the other hand, FastCopy 3 works fine.
But there is another clue. TOS and EmuTOS run from ROM, while FastCopy 3 runs from RAM. As ROM is accelerated, that could change things.

First hint: run EmuTOS from RAM to see what happens. In such version, the ROM is totally ignored, the whole EmuTOS lives in RAM.
- If it works, then we can assume that the trouble comes from ROM boost
- If it fails, then the only difference will be boosted CPU

Instructions:
Go there:
https://sourceforge.net/projects/emutos ... os/0.9.10/
And download emutos-prg-0.9.10.zip

Extract emutosuk.prg and put it into a floppy.

Start your ST with any ROM (TOS any version or EmuTOS).
Run emutosuk.prg from floppy.

Try to format a floppy and see what happens.

(then if necessary, we could build special EmuTOS binaries with extra debug output)
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by exxos » Tue Jan 08, 2019 10:04 pm

BlankVector wrote:
Tue Jan 08, 2019 9:57 pm
Hey, I'm back to business!
As I understand, you have that format error with accelerated CPU and ROM, right?
Hey! Yes, but we both made some progress... We did a patch to the code in TF's booster and he is running now.. So he doesn't get the error...

I found about a hour ago I have a problem with my design, so I need to do a new PCB before I can look into it more.. but I think I have a conflict with RW signal when I run fast-rom :roll:
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by exxos » Tue Jan 08, 2019 11:10 pm

Managed to squash the correct CPU layout in there.. Also routed RW,LDS,UDS via the PLD..

Also fixed a missing wire which stopped me from doing 8MHz/50MHz switching on the current board..

I also routed another pin to ST_DTACK.. simply because if anything like the blitter accesses ROM, then it would just "hang" as DTACK was only issued to the CPU before.. I don't think anything on the bus ever accesses ROM, but best to have that "Fix" in place just in case.

Need to add some CPU side pull-ups , as they are now in effect isolated from the pullups on the ST side.. Also need to add a pad for ROM_EN output.. WIll do all that Thursday.


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4MB STFM 1.44 FD- VELOCE+ 020 STE - 4MB STE 32MHz - STFM 16MHz - STM - MEGA ST - Falcon 030 CT60 - Atari 2600 - Atari 7800 - Gigafile - SD Floppy Emulator - PeST - HxC - CosmosEx - Ultrasatan - various clutter

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https://www.exxoshost.co.uk/atari/last/storenew/ - All my hardware mods for sale - Please help support by making a purchase.

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