Page 30 of 61

Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Posted: Sat Jan 19, 2019 11:41 pm
by rpineau
@PaulJ : I stand corrected :) (I'm always happy to be wrong, it means I'm learning :) ).

Glad to see other programmer being able to JTAG these devices.

Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Posted: Sun Jan 20, 2019 3:48 am
by PaulJ
Rpineau, not an issue, happy to be challenged. :)

Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Posted: Sun Jan 20, 2019 10:49 pm
by pakman
exxos wrote: Fri Jan 18, 2019 9:45 pm I can donate a board if anyone wants to build one up, but will need a Atmel programmer.
I have no idea how long it will take to debug the odd faults though.
I would like to get one!
PCB with 68000 SEC assembled, nothing else.
I will do my tests with a Lattice CPLD, where I have all tools (compiler, programmer) available.
Unfortunately not pin compatible, so it will need some extra wiring..

Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Posted: Sun Jan 20, 2019 10:59 pm
by exxos
pakman wrote: Sun Jan 20, 2019 10:49 pm I will do my tests with a Lattice CPLD, where I have all tools (compiler, programmer) available.
Unfortunately not pin compatible, so it will need some extra wiring..
I can send you a PCB.. but I think trying to force wire a different PLD would require much more effort than just creating a new PCB to fit your lattice PLD...

Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Posted: Fri Jan 25, 2019 1:21 pm
by exxos
So using a stencil is a bad idea on the PLD then...

Onto the fun part... :roll:

1.jpg
1.jpg (156.42 KiB) Viewed 4065 times

EDIT:

Looking a bit better now...

I really need to find a easier way of doing this stuff :roll:

4.jpg
4.jpg (119.48 KiB) Viewed 4060 times

So onto the CPU next.. then its in the US cleaner before I do anything else...

Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Posted: Fri Jan 25, 2019 3:02 pm
by exxos
Bit better results. I did solder a Videl on a Falcon last year this way without issues.

10.jpg
10.jpg (126.8 KiB) Viewed 4056 times

11.jpg
11.jpg (137.29 KiB) Viewed 4056 times

12.jpg
12.jpg (132.81 KiB) Viewed 4056 times

Still didn't go perfect though...

Did a crappy short video..




Its going in the US to clean up next before I get sticky fingers!

Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Posted: Fri Jan 25, 2019 4:14 pm
by PhilC
Is the clear stuff flux? I've not tried adding that to the inside, just solder paste but the needle for the paste is a bit too big, so I end up having to use desoldering braid to remove the extra.

Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Posted: Fri Jan 25, 2019 4:19 pm
by exxos
Forgottenmyname wrote: Fri Jan 25, 2019 4:14 pm Is the clear stuff flux?
yep.
Forgottenmyname wrote: Fri Jan 25, 2019 4:14 pm I've not tried adding that to the inside, just solder paste but the needle for the paste is a bit too big, so I end up having to use desoldering braid to remove the extra.
Yeah braid I use a lot of, and flux. I sent the last boosters off to be assembled for me as just can be doing without the hassle these days. I'm only doing this one myself as I got a bit of free time next week so want to see if I can diagnose the odd faults I keep seeing.

Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Posted: Fri Jan 25, 2019 4:36 pm
by PhilC
Well good luck then. Just ordered myself some Atmel Gals as my PAK still doesn't work and I know everything else on it does.

Hope you have better luck that I have so far.

Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Posted: Fri Jan 25, 2019 7:20 pm
by exxos
Now to see if the PLD is found.. then onto doing some simple test firmware (pinout is different than last build so have to do some tweaked firmware :roll: )

IMG_3756.JPG
IMG_3756.JPG (144.56 KiB) Viewed 4085 times



.. and some capacitor soldering voodoo...