V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by exxos » Mon Feb 04, 2019 3:01 pm

rubber_jonnie wrote:
Mon Feb 04, 2019 2:48 pm
I can understand, makes sense to get the other stuff in place, that will make a big difference.

I tried 64MHz.. Basically nope.. bombs on 104, 206 doesn't even try. I added in some more delays, but nope...

If I remember rightly, during my last tests, what I did was to literally just run the CPU faster on integer division test. I think it would basically lock up halfway through the test each time.

It may not necessarily be the CPU cannot run that fast, but the bus itself probably isn't anywhere near stable enough for it. Of course I already hit issues with 50MHz :(

Even so, even 50MHz is probably way too fast. Look at it that how fast they cycle is now, basically 20ns.

Even adding fast ram would mean we would need 10ns RAM which is hard to find and incredibly expensive.

I think talked about this previously that I was considering using a small bank of fast ram (10ns) to copy the ROM contents to during start-up. This is because the flash and ROM chips are basically too slow by themselves. So even adding flash is going to slow ROM access down.

In terms of fast ram, I think we will be pushed to even get 60ns RAM access speed. Which basically equates to 32MHz speeds. Realistically 32MHz would be a much better point to operate at.

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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by rubber_jonnie » Mon Feb 04, 2019 3:25 pm

It would make sense that the bus and maybe other components may not be happy when pushing way beyond the original 8Mhz speed.

I have to take my hat off to you that you've got so far with this.

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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by exxos » Mon Feb 04, 2019 4:58 pm

3 hours later...

At least making some progress...

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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by exxos » Tue Feb 05, 2019 2:58 pm

Still at it...

I gave the autorouter 3 layers to route in, nope, couldn't do it... and yet I got this routed manually before with just 1 layer.

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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by ijor » Tue Feb 05, 2019 6:36 pm

exxos wrote:
Mon Feb 04, 2019 3:01 pm
Even so, even 50MHz is probably way too fast. Look at it that how fast they cycle is now, basically 20ns.
Even adding fast ram would mean we would need 10ns RAM which is hard to find and incredibly expensive.

I think talked about this previously that I was considering using a small bank of fast ram (10ns) to copy the ROM contents to during start-up. This is because the flash and ROM chips are basically too slow by themselves. So even adding flash is going to slow ROM access down.
Is that a typo? 10ns RAM for a CPU running at 50MHz? Two RAM accesses per clock cycle?

I assume this is "fast ram" not managed by MMU. You could use static ram then. I think 45ns static Ram is fast enough for full speed without wait states. Should be widely available?
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by exxos » Tue Feb 05, 2019 6:49 pm

ijor wrote:
Tue Feb 05, 2019 6:36 pm
Is that a typo? 10ns RAM for a CPU running at 50MHz? Two RAM accesses per clock cycle?

I assume this is "fast ram" not managed by MMU. You could use static ram then. I think 45ns static Ram is fast enough for full speed without wait states. Should be widely available?
45ns SRAM + 10ns PLD delays is about 55ns cycle time. So CPU can run half that (twice as fast) lets just round it to 50ns, so 25ns CPU can run, at 50MHz thats 20ns per cycle (40ns until DTACK) , so basically the SRAM can run at full speed without wait states.

But for the point of RJ's reply, hes talking about Even faster CPU speeds 64MHz etc, would need even faster RAM, I just said 10ns as a arbitrary figure to make the point. it wasn't intended as a actual figure .
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by exxos » Tue Feb 05, 2019 7:55 pm

Still at it, but gonna have to call it a day soon, fingers hurting from all the clicking :(

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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by exxos » Wed Feb 06, 2019 12:35 am

Got 10 more wires to route, but will have to wait.. need to work out which pins to wire to the PLD first...

But its starting to look like a final PCB now :)

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The spec is 50MHz CPU, 50MHz 8MB Fast-RAM, 50MHz 8MB Flash-ROM.
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by ijor » Wed Feb 06, 2019 1:36 am

exxos wrote:
Tue Feb 05, 2019 6:49 pm
45ns SRAM + 10ns PLD delays is about 55ns cycle time. So CPU can run half that (twice as fast) lets just round it to 50ns, so 25ns CPU can run, at 50MHz thats 20ns per cycle (40ns until DTACK) , so basically the SRAM can run at full speed without wait states.
I see. I didn't know the PLD was that slow. If the PLD takes 10ns then you need something like 40ns or 35ns RAM for a 50MHz CPU. The CPU can run slightly faster than twice the RAM cycle. You have two and a half cycles from S2 to S7. It might be even possible to use an extra half cycle and start addressing the RAM on S1 if it's very important.

So are you going to implement shadow ram for copying the rom to ram?
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by exxos » Wed Feb 06, 2019 2:33 am

ijor wrote:
Wed Feb 06, 2019 1:36 am
.So are you going to implement shadow ram for copying the rom to ram?
No point is there.
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