V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by exxos » Wed Jan 08, 2020 9:37 pm

I'm just dumping this info here as will likely lose it , won't make any sense to anyone most likely, so just skip on ahead, nothing to see here :lol:

Measuring /AS(top) vs /WDAT(bottom) there is ~100ns delay between the 2. So likely 1x CLK8 cycle delay before /WDAT is issued.

AS_WDAT_100ns.png
AS_WDAT_100ns.png (100.78 KiB) Viewed 256 times


From /DTACK(top) to /WDAT(bottom) there is ~20ns delay. ( I zoomed in later to verify)

DT_WDAT_20ns.png
DT_WDAT_20ns.png (106.91 KiB) Viewed 256 times


From /AS (top) to /RDAT(bottom) there is ~75ns delay.. bizzare... Must be about 1 CLK16 cycle.

AS_RDAT_75.png
AS_RDAT_75.png (95.83 KiB) Viewed 252 times

From DT (top) to /RDAT (bottom) 0ns delay...

DT_RDAT_0ns.png
DT_RDAT_0ns.png (98.15 KiB) Viewed 251 times

EDIT:

I guess it could be that WDAT is based on the falling edge of CLK8, and RDAT is based on the rising edge of CLK8 :shrug: I guess it would add a bit of delay on the buffers between read and write cycles to stop them shorting each other out.

EDIT2:


CLK8 vs RDAT - Goes low about the fall of CLK8

CLK8_RDAT.png
CLK8_RDAT.png (111.07 KiB) Viewed 237 times

CLK8 vs WDAT - Glow low about the rise of CLK8

CLK8_WDAT.png
CLK8_WDAT.png (111.37 KiB) Viewed 237 times
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by PhilC » Wed Jan 08, 2020 9:45 pm

Makes perfect sense to me :shock:
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by exxos » Thu Jan 09, 2020 7:18 pm

exxos wrote:
Wed Jan 08, 2020 9:37 pm
Measuring /AS(top) vs /WDAT(bottom) there is ~100ns delay between the 2.
I do not get why that delay is even there in the first place.. In terms of writing to RAM, it would mean the DRAM would not get the data from the CPU until 100ns later ( plus the delay of the LS244 buffers).

So I swapped out the 120ns DRAMs for 100ns ones to make things easier..

This benchmark is basically the original (baseline test)
IMG_4799.JPG
IMG_4799.JPG (63.6 KiB) Viewed 227 times


This benchmark is with a separate delay on ST_RAM WRITE DTACK. basically 4x 50MHz clocks ~ 80ns.

IMG_4802.JPG
IMG_4802.JPG (75.74 KiB) Viewed 227 times
Now if we assume 20ns delay on the LS244 ( will likely be a bit quicker but I am building in some margin of error into this figure anyway) we end up with 100ns! if I take away 20 ns, the machine just turned into a crash generator, because basically it is running the RAM at 80ns.

Basically mean, assuming a delay of 100ns on the MMU, plus 20 on the buffers (120ns) and a 8MHz cycle time of 250ns, this means the DRAM would have to be (250ns - 120ns) 130ns or faster. Now I have seen 150ns chips so likely it's doable. Basically the figures do generally work out as expected. I would assume RAM slower than 150 ns was never fitted in the ST range ?

So what the heck is this all about ? basically I am trying to speed up RAM access without overclocking the MMU. In terms of Write cycles, the CPU databus simply goes through the LS244 buffers to the DRAM, MMU really does not have anything to do with speed at that point.

The above benchmarks may not look very interesting, but it proves the point that ram access does appear to be speeding up.. The RAM speed test would likely show any speed improvement until we hit double speed of 200%. This is basically because we cannot fit 2 RAM accesses in the same time frame unless the RAM is running at 200% speeds. So what I assume is happening is that the RAM cycle completes slightly early, and it is able to start a ROM cycle sooner, which is slightly increasing the scores in the benchmarks.

The problem is this odd 100ns delay. Because the MMU is controlling who has access to RAM, we cannot simply bypass it, as it may actually need to be there at some point because of shifter accesses to RAM.So it looks like I may have hit a brick wall with this direction :cry:

EDIT:
Part of the delay on write might be down to the delayed RW on the 68000 itself.. so need to look into that timing as well ...

EDIT2:
I also tried speeding up the RAM READ, ended up as 7 clocks delay ( 120ns). Most scores went up about 2%. Int-div was the largest one which jumped to 512% from 506%.
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by exxos » Thu Jan 09, 2020 8:58 pm

I thought I would do some tracing on the clocks vs WDAT and RDAT vs the 2MHz clock..

So I guess this explains some things..

4w.png
4w.png (162.39 KiB) Viewed 203 times

WDAT / RDAT are in sync with the 2MHz clock. Which must be the clock used to determine if the CPU gets RAM time or not. But because of all the wakeupstates, I think this is throwing things out all over the place.

The CPU will set /AS low and request RAM, but its gotta wait for the 2MHz clock, which can't really be in sync with the 8MHz clock :roll: I guess I could generate a new 2MHz clock, but likely that would knock onto screwing something else up anyway. The only other possible thought would be to bypass the MMU's buffer control lines and re-generate them in the PLD instead :roll:

EDIT:
So my brain has gone to sleep I think. The CPU can set /AS low at any point in the 2MHz cycle, basically random. And the MMU is not going to give access to RAM until the 2 MHz signal goes high. As soon as it does go high, the MMU enables the buffers, so basically we might as well say no delays there other than the buffer itself and DRAM speed.

So with 2MHz cycle time being 500ns. Thats 250ns HI & 250ns low. CPU at 8MHz has a cycle time of 250ns, so it can *just* do a RAM access in that time slot. In theory, 100ns RAM with a CPU running 50Mhz, it should already be accessing RAM at double speed at least. As 100ns x 2 = 200ns, and we have a 250ns "window" to access RAM. So why is RAM access not behaving ?

EDIT2:

Currently I have on RAM delays with 100ns RAM:
READ: 7 x 20ns = 140ns
WRITE: 4x20ns = 80ns

I tested 2MHz vs WDAT and only see it going low once :roll: This is with a 7 clocks elay (140ns) on both read and write.

8wdat.png
8wdat.png (137.06 KiB) Viewed 185 times
I even checked RDAT , still 156ns cycle time. I don't see RDAT follow immediately after WDAT either. Really its about 31ns to slow. So 100ns - 31 = 69ns (or 70ns RAM speed) to get the cycle to fit it seems :roll: Even so, whats stopping the next RAM cycle from starting anyway :stars:

EDIT3:
I put back 80ns WRITE time, and the scope shows 120ns now. oddly RDAT now reads 200ns.
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by exxos » Fri Jan 10, 2020 11:00 am

I've been thinking its likely the DRAM RAS/CAS which are likely in a internal state machine in the MMU causing trouble. I was reading through this document about the DRAM operation https://compas.cs.stonybrook.edu/~nhona ... dramop.pdf Where basically the address line inputs to the RAM seem to be multiplexed based on RAS & CAS. These timings will be hardwired into the MMU. So even though the buffers and CPU can run at much higher speeds, the MMU is simply not going to access the data on the RAM any faster without overclocking the MMU itself.

The only possible workaround would be to use SRAM. This would also entail building new logic to control the buffers. Scoping out some signals on the MMU, it seems that the /DEV pin is active when accessing the floppy, and /RAM is active when accessing the RAM, and I would assume /DMA is active when accessing bus masters such as the blitter. However I don't actually understand why there is even three signals for this as an signal would surely be enough to determine if the shifter is accessing the bus, or everything else such as CPU, or blitter. Though as the MMU is also controlling RAM for video, however it is translating counters to a RAM address would likely be working against me in trying to just have a simple SRAM and setup :roll:

So we are basically back to building a new MMU in order to speed up RAM access,But with no solid diagram to even work from it is just a dead end :roll: I was looking for alternative ways of speeding up RAM instead of overclocking the MMU as it has various issues with wakeup states interfering with various timings. Though it seems the over clock is probably the only alternative to trying to build a new MMU :roll:

EDIT:

I think trying the suska MMU core is the next step. if it works "out of the box" Should allow is to increase ram speed a lot easier.
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by exxos » Fri Jan 10, 2020 6:11 pm

Crappy video of the first test run of software switching on the SEC booster :)

After switching several times the machine locks up, but at least the concept is working so far :)





..And yes I used flashy clock software to control the SEC booster as to lazy to start a new app :)


EDIT:

Clock switching is a lot better now. Simulation shows this... I can't get my scope to lock onto anything but the 50mhz to 8mhz cycle :roll:

Capture.JPG
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clksx.png
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by Icky » Sat Jan 11, 2020 2:25 pm

Its like the SEC Booster and H4 were designed to be together ;)

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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by exxos » Sat Jan 11, 2020 2:32 pm

Icky wrote:
Sat Jan 11, 2020 2:25 pm
Its like the SEC Booster and H4 were designed to be together ;)
Almost ;)


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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by PhilC » Sat Jan 11, 2020 3:08 pm

Now that looks good to me.

Is that the correct socket to put it in or can it go into any of them?
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by Icky » Sat Jan 11, 2020 3:28 pm

PhilC wrote:
Sat Jan 11, 2020 3:08 pm
Now that looks good to me.

Is that the correct socket to put it in or can it go into any of them?
It can go in any of them. Just remember to take out the PLCC CPU :)

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