TFMSX Arrives

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terriblefire
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Re: TFMSX Arrives

Post by terriblefire »

I ordered up the TFMSX rev1. I got preassembly but excluded the arm and CPLDs because they were going to add 300 quid for 5 of each to the order!!!

I can reclaim the r0 arms and I have lots of 288s. Could do with finding a source of the F722RET6s
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indicates how much hurting you shall receive."
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arkadiusz.makarenko
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Re: TFMSX Arrives

Post by arkadiusz.makarenko »

terriblefire wrote: Sat Sep 25, 2021 1:04 pm I ordered up the TFMSX rev1. I got preassembly but excluded the arm and CPLDs because they were going to add 300 quid for 5 of each to the order!!!

I can reclaim the r0 arms and I have lots of 288s. Could do with finding a source of the F722RET6s

Yes ... They should be availiable in next quarter.
ST is focusing with production of <90nm MPUs, so we should not expect F0, F1, F2 i F3 any time soon.
Fortunately F7 are <90nm, and in active production. Here there is issue with LQFP.

I do have untouched 2 spare f722, and like 2 which I can very easily repurpose.
@kulamario do you have few spare by any chance?
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Re: TFMSX Arrives

Post by terriblefire »

arkadiusz.makarenko wrote: Sat Sep 25, 2021 1:41 pm
terriblefire wrote: Sat Sep 25, 2021 1:04 pm I ordered up the TFMSX rev1. I got preassembly but excluded the arm and CPLDs because they were going to add 300 quid for 5 of each to the order!!!

I can reclaim the r0 arms and I have lots of 288s. Could do with finding a source of the F722RET6s

Yes ... They should be availiable in next quarter.
ST is focusing with production of <90nm MPUs, so we should not expect F0, F1, F2 i F3 any time soon.
Fortunately F7 are <90nm, and in active production. Here there is issue with LQFP.

I do have untouched 2 spare f722, and like 2 which I can very easily repurpose.
@kulamario do you have few spare by any chance?
I think i have a few on unbuilt TF risers also. So defo have enough for the run of 5 i'm doing
———
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indicates how much hurting you shall receive."
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arkadiusz.makarenko
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Re: TFMSX Arrives

Post by arkadiusz.makarenko »

I started investigating DMA on stm32.
I think it finally clicked, as I always looked at DMA settings straight away, and was overwhelmed with configuration, and wasn't able to finish it.
Instead I should look at Timers and DMA configuration. As it is timer which triggers DMA action (which is from stm32 perspective simple MemToMem transfer)

EDIT
It is actually not standard thing as CubeIDE doesn't allow GUI configuration of what I think I need. It only allows periferia to memory.
Saying this HAL has all configured structs and stuff in place. I just need to configure right timer in right way and right DMA stream/channel, and should work... But yes very specific timers and gpio pins are needed to make it happen.
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Re: TFMSX Arrives

Post by kulamario »

arkadiusz.makarenko wrote: Sat Sep 25, 2021 1:41 pm
terriblefire wrote: Sat Sep 25, 2021 1:04 pm I ordered up the TFMSX rev1. I got preassembly but excluded the arm and CPLDs because they were going to add 300 quid for 5 of each to the order!!!

I can reclaim the r0 arms and I have lots of 288s. Could do with finding a source of the F722RET6s

Yes ... They should be availiable in next quarter.
ST is focusing with production of <90nm MPUs, so we should not expect F0, F1, F2 i F3 any time soon.
Fortunately F7 are <90nm, and in active production. Here there is issue with LQFP.

I do have untouched 2 spare f722, and like 2 which I can very easily repurpose.
@kulamario do you have few spare by any chance?
3pcs or 4pcs not sure now
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arkadiusz.makarenko
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Re: TFMSX Arrives

Post by arkadiusz.makarenko »

I am doing some prep for this stm32 firmware.
I am thinking of dropping HAL libraries for all peripherals expect USB stack (as it is too complex and writing new usb stack would take like a year or so), as it is far too bulky and confusing. It was great to start with it as it didn't require too much knowledge about underlying hardware, but has one big issue, it is just slow as hell.
Fortunately stm32 offers something called LL (low-layer drivers), which is almost as fast as working directly on registers, and there is no need to do bitwise operations on registers as it is covered by macros and functions. Still options available on configuration will be visible in function and macro headers, so much less time will be needed to spend looking for stuff in reference manual. Downside is that I need to learn complete new naming conventions, but I guess it will be worth at the end.
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Re: TFMSX Arrives

Post by terriblefire »

I guess my vision (brainfart?) for this is ..

The CPLD holds a bunch of registers for the ARM that act like ram. Whenever the Z80 accesses the keyboard the CPLD serves up these.

The arm on the other hand can set them with the lines we have available as things change. This way the z80 should never wait for data.

Might be pushing the CPLD to the limit a bit on this one.
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indicates how much hurting you shall receive."
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Re: TFMSX Arrives

Post by arkadiusz.makarenko »

How much time do you think is acceptable to wait? How much time do I have on arms side?

Definitely DMA with GPIO is way forward even to replace few cycles.

EDIT: I will make it work even if I had to bring those bits with my own bare hands! :D
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Re: TFMSX Arrives

Post by terriblefire »

Z80 cycles are a lot slower than Amiga ones..... math time

2 * 1.0 / 3.58 Mhz = 558ns

This is the response time if there is no waiting at all. I believe the Z80 does a refresh after each memory access too. I think for IO an extra wait cycle would probably be acceptable if not ideal.
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indicates how much hurting you shall receive."
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Re: TFMSX Arrives

Post by arkadiusz.makarenko »

terriblefire wrote: Thu Sep 30, 2021 8:44 am Z80 cycles are a lot slower than Amiga ones..... math time

2 * 1.0 / 3.58 Mhz = 558ns

This is the response time if there is no waiting at all. I believe the Z80 does a refresh after each memory access too. I think for IO an extra wait cycle would probably be acceptable if not ideal.
EXTI Latency is just below 200n, this would give me about 50-60 cycles of processing time on stm32.
GPIO interrupts on this stm are shared between ports and grouped for some pins (pin 0-4 on each port have own interrupt, and pins 5-9 and 10-15 on each port have grouped interrupt).
So it may be just enough? I guess we will find out soon.

EDIT:
2 cycles - 1us, then there is enough time to do whatever is needed.
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