V2.5 BOOSTER CURRENT PROTOTYPE STATUS

Help & information about the V2.5 booster.
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exxos
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS

Post by exxos » Mon May 21, 2018 9:22 pm

rpineau wrote:
Mon May 21, 2018 9:08 pm
Is the E clock running properly ?
Looks good on scope..


rpineau wrote:
Mon May 21, 2018 9:08 pm
AVEC should definitely do something on interrupt from the keyboard. But if we can't write to the ACIA it probably doesn't trigger interrupt yet.
So it's really around VMA/VPA
No idea, I keep trying things, but no luck..

If I keep pressing reset, I see VMA pulse low.. though I half recall it does pulse more than VPA.. will have to re-read my notes tomorrow..

VPA I have trouble seeing any pulses.. but thats generated from GLUE anyway...

I don't get why diag-cart says DMA time out.. has nothing to do with CPU really :roll:
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS

Post by rpineau » Mon May 21, 2018 9:26 pm

DMA stuff is done in bus master mode (driven by GLUE). So when there is a DMA transfer the CPU is not bus master. So that timeout tells us there is potentially something wrong with BR/BG/BGACK login to the SEC CPU.

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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS

Post by exxos » Mon May 21, 2018 9:48 pm

rpineau wrote:
Mon May 21, 2018 9:26 pm
DMA stuff is done in bus master mode (driven by GLUE). So when there is a DMA transfer the CPU is not bus master. So that timeout tells us there is potentially something wrong with BR/BG/BGACK login to the SEC CPU.
ST_BR, CPU_BG,CPU_BR seem to be always high... so nothing requesting the bus yet...
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS

Post by exxos » Tue May 22, 2018 5:01 pm

So after talking to Rodolphe, we finally figured out the problem and we are now working :)

I guess it would help if I had actually built a 020 booster, as this chip wires up like it, so actually had a line missing in my code process VMA cycles correctly... Anyway it is now working at the stock 8Mhz and it has been running for the past couple of hours in GB6.

So next up, I need to solder a 32Mhz OSC onto the board and start adapting the code to run at the higher clock speeds. I already did a lot of research on this, so hopefully I can add the changes without too much trouble to the current code..

The good thing is now, I don't have to worry about E-clock as it is internally generated in the PLD. So I can literally jump to any speed and E-clock will always run at the proper speeds :)
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS

Post by exxos » Thu May 24, 2018 8:20 pm

Finally some more or less sensible benchmarks running at 16Mhz.


First test was more failsafe firmware...

t1.jpg
t1.jpg (104.75 KiB) Viewed 247 times
We can see the CPU is running at 16MHz due to the int-div being 189%.

Next up is 20 MHz with tighter timings....
t2.jpg
t2.jpg (109.38 KiB) Viewed 247 times
We can see the jump in integer division to 231%..

However, the ROM speed is actually slower than it should be.. Considering it is running at 20MHz.. It is actually fractionally slower than the V1.5 booster running at 16MHz..
16CPUROM_result.png
16CPUROM_result.png (4.42 KiB) Viewed 247 times

Though the problem with the current prototype is that I have not got a on-board ROM yet. Trying to sync DTACK is a little bit of a nightmare while using GLUE for the normal decoding.. So ROM speed is actually slower than would be on a more dedicated board.

I am currently not too concerned about this, as this prototype is to benchmark the fastest possible speed of this CPU... So only really concerned with stability and integer division... So hopefully I can try 32MHz soon...
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS

Post by exxos » Mon May 28, 2018 1:38 pm

So the past few days I have working a 32MHz OSC, BUT, GB6 crashes with 4 bombs when it turns of the ACIA interrupts :roll: I did have some issues like this before which turned out I needed to delay VPA to the CPU.. but that was with a normal 68000.. AVEC & VMA & E are emulated on the SEC (just like the 020 does). So there should be no reason this problem..

It does however all work fine at 25MHz. So obviously the CPU running faster still out 32MHz is causing something to trip up.. I have tried everything I can think of adding delays and speeding things up, there is combinations of timings, and just refused to work at 32MHz.

I can run GB4 with all tests perfectly, so it is not like it is not stable.. Though the 4 bombs is consistent, so I think there must be some issues with vector addresses, maybe relating to the MFP. I can only think the MFP manually puts a vector on the address bus and the CPU reads this address too fast you and jumped to a vector which is on used and basely causes the bombs and the crash.

I don't really know how to determine expected scheme is being useful than the actual RAM address being accessed.. I did try programming in those addresses, but in reality those addresses are probably wrong to start with..

In any case, I'm completely at a loss what the problem is, and not really sure how to solve this :(


EDIT:
Aside from the ACIA issues, I have tried 40MHz and just get a row of bombs..I guess it could be possible that the CPU simply cannot run at 40Mhz. I found the PLCC 68000 topped out at about 38MHz..
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS

Post by exxos » Tue May 29, 2018 3:30 pm

After about 50 hours of experimenting I finally got it to run!! :o :o :shock: :shock:

I had a lot of ideas to work through it seems the problem lies in AVEC being triggered twice during a VPA cycle.

I was using VMA as a delay start of the AVEC cycle but also added in a chain of delays which would basically only allow AVEC to trigger once.. But the some odd reason the floppy drive light would come on and I would just end up with a white screen..

Then I had an idea as I was using VMA, simulated based on E-clock, I thought I would just reset the E-clock FF's like this...

Code: Select all

QA.AR = !RESET # CPU_AS;
QB.AR = !RESET # CPU_AS;
QC.AR = !RESET # CPU_AS;
QD.AR = !RESET # CPU_AS;
And shockingly this seems to have solved the problem... Now I just have to really work out exactly why :lol: :roll:

It could also be ACIA is still holding data on the bus while the CPU is trying to do something else, so clearing E-clock likely disable the ACIA.. So a few things yet to investigate..
yay.jpg
yay.jpg (138.59 KiB) Viewed 168 times
Of course the scores are pretty messed up, but this is due to very slow delay lines while I was debugging.. But we can see on integer division that the CPU is running at 32MHz.. But most importantly it actually worked!!

Now I need a beer! :lol:

EDIT:

So some more testing, the VMA delay chain was removed from AVEC and set with 2x!CLK8 instead and this to test OK.. So next up I ran E,VMA at double speed (16MHz) and this did seem to partly work but was unstable and crashed after the first test.. So we could be hinting that there is a bus conflict right after the AVEC cycle likely with the ACIA chips.

EDIT2:

Code: Select all

!AVEC.CK = !CLK8;
!AVEC.D =  AV1 & ST_DTACK & !CPU_AS;

AV1.CK = !CLK8;
AV1.D = FC2 & FC1 & FC0 & !VPA  & A19 & A18 & A17 & A16 ;
Added in ST_DTACK & CPU_AS to AVEC.... Now it seems to be running stable now..
So possible there are two problems.. ACIA causing bus conflict due to being driven from the 8MHz.. And also re-triggering of AVEC..
Now to do some soak testing :)
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS

Post by Atarian Computing » Tue May 29, 2018 4:10 pm

Sweeeet

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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS

Post by rpineau » Tue May 29, 2018 5:35 pm

Nice.
This kind of make sense also as on a 68000 the CPU sync itself to the E clock before starting the access (and may be before asserting VMA) when VPA is asserted.
On a 68020 and 68SEC000 it doesn’t know about the E clock. So reseting the E clock at the beginning of a CPU access probably help syncing the E clock to the CPU (aka the other way around from what a 68000 would do).
Nice finding !.

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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS

Post by exxos » Tue May 29, 2018 9:27 pm

40MHz.. Can be seen via integer division 8-) 1% higher than my best on the PLCC on the STE ages ago.. That was unstable anyway.. So far the SEC CPU seems happy...

The next issue is my monitor seems be losing sync intermittently.. I do not think this is a bad cable though as it was working fine a few moments ago on 32MHz.. So maybe a issue with the V&H sync vectors... :shrug:
40mhz.jpg
40mhz.jpg (113.17 KiB) Viewed 138 times

EDIT: think its a bad connection on the MB somewhere causing the sync issues...
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