TF CD32 Riser Revision 2 Design Complete

68030 + SDRAM + IDE

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arkadiusz.makarenko
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Re: TF CD32 Riser Revision 2 Design Complete

Post by arkadiusz.makarenko » Sat Oct 17, 2020 9:25 pm

terriblefire wrote:
Sat Oct 17, 2020 9:15 pm
arkadiusz.makarenko wrote:
Sat Oct 17, 2020 8:58 pm
CPLD source code: https://github.com/arkadiuszmakarenko/T ... v1XC9572XL
STM32f722 (still can fit in stm32f730) - https://github.com/arkadiuszmakarenko/TFRiserRev1F722

Time for a bottle of wine.
boards are 80% done manufacturing.

We have keyboard and mouse support? :)
Keyboard yes (tidied up the code a little and fixed reset issues)

Mouse and gamepads.... I have mouse XY delta and button states, gamepad readings on ARM side. Now still don't have clue what to do with it... yet.
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Re: TF CD32 Riser Revision 2 Design Complete

Post by terriblefire » Sat Oct 17, 2020 9:53 pm

arkadiusz.makarenko wrote:
Sat Oct 17, 2020 9:25 pm
Mouse and gamepads.... I have mouse XY delta and button states, gamepad readings on ARM side. Now still don't have clue what to do with it... yet.
Mouse should simply supply JOY0DAT the way the MiST setup does. On this riser it will be 2 reads (2 bytes of a word) but you can anticipate the second read in the arm as the system will always do these sequentially. I guess there might be code out there that reads them byte by byte?

http://amigadev.elowar.com/read/ADCD_2. ... e0038.html

The joypad buttons are a bit more complex on the CD32.

Code: Select all

;//=//=//=//=//=//=//=//=//=//=//=//=//=//=//=//=//=//=//=//=//=//=//=//=//=//



	IFND	HARDWARE_CUSTOM_I

_custom		EQU	$dff000
_ciaa		EQU	$bfe001
_ciab		EQU	$bfd000

	ENDC


	INCDIR	Includes:

	INCLUDE hardware/custom.i
	INCLUDE	hardware/cia.i




;in d0 == 0 - port 0
;      == 1 - port 1
;

; this is out

;JPB_JOY_RIGHT		= 0
;JPB_JOY_LEFT		= 1
;JPB_JOY_DOWN		= 2
;JPB_JOY_UP		= 3

;JPB_BUTTON_PLAY	= $11
;JPB_BUTTON_REVERSE	= $12
;JPB_BUTTON_FORWARD	= $13
;JPB_BUTTON_GREEN	= $14
;JPB_BUTTON_YELLOW	= $15
;JPB_BUTTON_RED		= $16
;JPB_BUTTON_BLUE	= $17


joystick	movem.l	d1-d7/a0-a1,-(sp)

		lea	_custom,a0
		lea	_ciaa,a1

		moveq	#1,d0			;PORT 1

		
		moveq	#CIAB_GAMEPORT0,d3	;red button ( port 0 )
		move.w	#10,d4			;blue button ( port 0 )
		move.w	#$f600,d5		;for potgo port 0
		moveq	#joy0dat,d6

		tst.l	d0
		beq.b	.direction

		moveq	#CIAB_GAMEPORT1,d3	;red port 1
		moveq	#14,d4			;blue port 1 
		move.w	#$6f00,d5		;for potgo port 1
		moveq	#joy1dat,d6		;port 1
		
		
.direction	moveq	#0,d7
		
		move.w	(a0,d6.w),d0		;get joystick direction

		move.w	d0,d1
		lsr.w	#1,d1
		eor.w	d0,d1

		btst	#8,d1			;check joystick up
		sne	d7
		add.w	d7,d7

		btst	#0,d1			;check joystick down
		sne	d7
		add.w	d7,d7

		btst	#9,d0			;check joystick left
		sne	d7
		add.w	d7,d7

		btst	#1,d0			;check joystick right
		sne	d7
		add.w	d7,d7

		swap	d7

	;two buttons
	
		btst	d4,(potinp,a0)		;check button blue
		seq	d7
		add.w	d7,d7

		btst	d3,(ciapra,a1)		;check button red
		seq	d7
		add.w	d7,d7

		and.w	#$0300,d7
		asr.l	#2,d7
		swap	d7
		asr.w	#6,d7


	; read buttons from CD32 pad

		bset	d3,(ciaddra,a1)		;set bit to out at ciapra
		bclr	d3,(ciapra,a1)		;clr bit to in at ciapra

		move.w	d5,(potgo,a0)

		moveq	#0,d0
		moveq	#8-1,d1
		bra.b	.in

.loop		tst.b	(a1)
		tst.b	(a1)
.in		tst.b	(a1)
		tst.b	(a1)
		tst.b	(a1)
		tst.b	(a1)
		tst.b	(a1)
		tst.b	(a1)

		move.w	(potinp,a0),d2

		bset	d3,(ciapra,a1)
		bclr	d3,(ciapra,a1)

		btst	d4,d2
		bne.b	.next

		bset	d1,d0

.next		dbf	d1,.loop

		bclr	d3,(ciaddra,a1)		;set bit to in at ciapra

		move.w	#$ffff,(potgo,a0)

		swap	d0

		or.l	d7,d0

		movem.l	(sp)+,d1-d7/a0-a1

		rts
Maybe @chucky can update diagrom for cd32 buttons. :)
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Re: TF CD32 Riser Revision 2 Design Complete

Post by arkadiusz.makarenko » Sat Oct 17, 2020 11:50 pm

I have joy0/1data already formatted. So it should be starting point.

I have few questions.
1. Does punt stop response from chipset?
2. How do I exacly push 16 pits via 8 bits databus?
3. Do I just decode address and set interrupt and handle it from arm?

...where do I even start... ah ok bottle of rum :D
Do not trust people. They are capable of greatness.
~ Stanislaw Lem

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Re: TF CD32 Riser Revision 2 Design Complete

Post by terriblefire » Sun Oct 18, 2020 12:52 am

arkadiusz.makarenko wrote:
Sat Oct 17, 2020 11:50 pm
I have joy0/1data already formatted. So it should be starting point.

I have few questions.
1. Does punt stop response from chipset?
2. How do I exacly push 16 pits via 8 bits databus?
3. Do I just decode address and set interrupt and handle it from arm?

...where do I even start... ah ok bottle of rum :D
1. PUNT tells the chipset to STFU yes. But watch out because the TF330/328 asserts PUNT too and will expect you to STFU (which is why punt lines are split).
2. The 68030/020 does dynamic bus sizing. So if you reply with 8 bits and it wants 16 it will ask for another 8 (i.e. do another cycle).
- The second cycle A0 will be high. This is why i say you can anticipate it.
- You reply with 8 bits by asserting DSACK0, for 16 bits it would be DSACK1, for 32 bits both.
(but since you only have 8 bits of data bus you alway reply with 8 bits).
3. Yeah decode the range down to A6 in this case.. i.e A[23:6] == {16'hdff0, 2'b00}
- this will let you decode all the chipset registers you need with one decode as you can access all the remaining address pins in the arm.
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Re: TF CD32 Riser Revision 2 Design Complete

Post by arkadiusz.makarenko » Sun Oct 18, 2020 9:44 pm

I have some issues. I can see that even setting up like this

Code: Select all

output [1:0] DSACK,
assign DSACK = (rtc_int||joy_int)?(intsig7_int?2'b10:2'b11):2'bzz ;
I am never asked for second section of register, so I can replace only higher section.
Maybe my INTSIG7 pulse which setup DSACK is too long and covers both reads?

code for reference

Code: Select all

wire rtc_decode = A[23:16] == 8'b1101_1100; //RTC registers at $DC0000 - $DCFFFF read,
wire JOY0DATA = A[23:0] == 24'hDFF00A;
wire JOY0DATB = A[23:0] == 24'hDFF00B;
wire JOY1DATC = A[23:0] == 24'hDFF00C;
wire JOY1DATD = A[23:0] == 24'hDFF00D;

wire punt_int = rtc_decode|JOY0DATA|JOY0DATB|JOY1DATC|JOY1DATD ;



reg rtc_int;
reg joy_int;
reg intsig7_int;


always @(posedge CLKCPU_A) begin 
	rtc_int <= PUNT_IN & rtc_decode ;
	joy_int <= PUNT_IN & (JOY0DATA||JOY0DATB||JOY1DATC||JOY1DATD);
	intsig7_int<= INTSIG7;
end



// punt works by respecting the accelerator punt over our punt.
assign PUNT_OUT = PUNT_IN ? punt_int ? 1'b0 : 1'bz : 1'b0;
assign INTSIG2 = rtc_int;    
assign INTSIG8 = joy_int;  

assign DSACK = (rtc_int||joy_int)?(intsig7_int?2'b10:2'b11):2'bzz ;

assign INTSIG3 = A[3];
assign INTSIG5 = A[5];
assign INTSIG1 = A[0];


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Re: TF CD32 Riser Revision 2 Design Complete

Post by terriblefire » Sun Oct 18, 2020 10:06 pm

Dont decode A[0] or you will never see the odd byte request.

e.g.

Code: Select all

wire JOY0DATA = A[23:1] == {20'hDFF00, 3'b101}; 
wire JOY1DATA = A[23:1] == {20'hDFF00, 3'b110}; 
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Re: TF CD32 Riser Revision 2 Design Complete

Post by terriblefire » Sun Oct 18, 2020 10:16 pm

Also A[0] is mapped to pin 24 on the arm already btw.
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Re: TF CD32 Riser Revision 2 Design Complete

Post by terriblefire » Sun Oct 18, 2020 10:22 pm

Im still worried why you arent using flip flops. You'll have issues without them for sure.

http://www.asic-world.com/verilog/verilog_one_day3.html
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Re: TF CD32 Riser Revision 2 Design Complete

Post by arkadiusz.makarenko » Mon Oct 19, 2020 1:00 am

terriblefire wrote:
Sun Oct 18, 2020 10:16 pm
Also A[0] is mapped to pin 24 on the arm already btw.
That was just desperate way of looking for A0 value.
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Re: TF CD32 Riser Revision 2 Design Complete

Post by arkadiusz.makarenko » Mon Oct 19, 2020 1:03 am

terriblefire wrote:
Sun Oct 18, 2020 10:22 pm
Im still worried why you arent using flip flops. You'll have issues without them for sure.

http://www.asic-world.com/verilog/verilog_one_day3.html
So writing code like this is not enough?

Code: Select all

always @(posedge CLKCPU_A) begin 
	rtc_int <= PUNT_IN & rtc_decode ;
	dsact_int <= PUNT_IN & (rtc_decode|JOY0DATA|JOY1DATA);
	joy_int <= JOY0DATA|JOY1DATA;
	intsig_int <= INTSIG7;
end
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~ Stanislaw Lem

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