Moderators: terriblefire, Terriblefire Moderator
I am struggling with access to JOY0/1DAT_L section of address. Still don't know whyterriblefire wrote: ↑Sun Oct 18, 2020 10:06 pm Dont decode A[0] or you will never see the odd byte request.
e.g.
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wire JOY0DATA = A[23:1] == {20'hDFF00, 3'b101}; wire JOY1DATA = A[23:1] == {20'hDFF00, 3'b110};
You also MUST use an always block for the DTACK.arkadiusz.makarenko wrote: ↑Mon Oct 19, 2020 9:05 am What I think I need to do is to Arm ack (intsig7) transform to single pulse on rising edge of intsig7.
I don't know how long it takes for intsig7 signal to set and then reset, it can cover both cycles of data read.
So it may trigger arm interrupt, but I double check if interrupt is still pending, in this case I wouldn't see second read.
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always @(posedge CLKCPU_A or posedge AS) begin
if (AS == 1'b1) begin
DSACK_INT <= 2'b11;
end else begin
DSACK_INT <= ... your logic ...
end
end
assign DSACK ? PUNT_INT ? 2'bzz : DSACK_INT;
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wire rtc_decode = A[23:16] == 8'b1101_1100; //RTC registers at $DC0000 - $DCFFFF read,
wire JOY0DATA = A[23:1] == {20'hDFF00, 3'b101};
wire JOY1DATA = A[23:1] == {20'hDFF00, 3'b110};
wire punt_int = rtc_decode|JOY0DATA|JOY1DATA;
reg rtc_int;
reg joy_int;
reg intsig_int;
reg dsact_int;
reg punt_ok;
always @(posedge CLKCPU_A) begin
rtc_int <= PUNT_IN & rtc_decode ;
punt_ok <= PUNT_IN & punt_int;
joy_int <= PUNT_IN & (JOY0DATA|JOY1DATA);
end
always @(posedge CLKCPU_A or posedge AS20) begin
if (AS20 == 1'b1) begin
intsig_int <= 1'b1;
end else begin
if (INTSIG7 == 1) begin
intsig_int <= 1'b0;
end else begin
intsig_int <= 1'b1;
end
end
end
// punt works by respecting the accelerator punt over our punt.
assign PUNT_OUT = PUNT_IN ? ( punt_int ? 1'b0 : 1'bz) : 1'b0;
assign INTSIG2 = rtc_int;
assign INTSIG8 = joy_int;
assign DSACK = punt_ok?{1'b1, intsig_int}:2'bzz ;
assign INTSIG3 = A[3];
assign INTSIG5 = A[5];
terriblefire wrote: ↑Tue Oct 20, 2020 9:15 am When you word read address 0xDF0000 (lets say there is a word at this address 0x1234).
0x12341234 is put on the full data bus.
If you DSACK0 (8 bits) it will read 0x12 (D[31:24]) for this address.
It will then ask for a byte at 0xDF0001
0x34343434 is put on the data bus.
If you DSACK0 it will use the data bus bits D[31:24], if you DSACK1 it will use the data bus bits D[23:16].
Its dyamically sizing the bus. All you need to do is understand its BIG endian (the arm is LITTLE endian).
EDIT: i.e. before you send data to the CPLD do htons() on it.