TF CD32 Riser Revision 2 Design Complete

[arkadiusz.makarenko]

A simpler test would be to use diagrom to probe an area of RAM like B00000 ...

make the arm respond with the lower 5 bits address bits being sent.

that way you should see

00 01 02 03 04 05 06 07 08 .... up to 1F

then it repeats.

Decode like B000xx

I did following test.
ARM repeat address back on read. A[5:0]

When I decode 0xB000xx I see as follows

20201020_133142.jpg (323.29 KiB) Viewed 2365 times

But when I try the same trick on JOY0/1DATA I see this

20201020_133217.jpg (304.7 KiB) Viewed 2365 times

Edit.
Is it some kind of clash with chipset?

[terriblefire]

Are you asserting punt?

[arkadiusz.makarenko]

Are you asserting punt?

I hope so ...

Code: Select all

wire rtc_decode = A[23:16] == 8'b1101_1100; //RTC registers at $DC0000 - $DCFFFF read,
wire Memory_decode = A[23:8] == {16'hB000}; 
wire JOY1DATA = A[23:3] == {20'hDFF00, 1'b1}; 

wire punt_int = rtc_decode|Memory_decode|JOY1DATA ;

assign PUNT_OUT = PUNT_IN ? ( punt_int ? 1'b0 : 1'bz) : 1'b0;

edit:
I did try this as well, just to be 100% sure that I am not missing obvious.

Code: Select all

assign PUNT_OUT = PUNT_IN ? ( punt_int ? 1'b0 : 1'b1) : 1'b0;

[terriblefire]

What is your DTACK term look like??

[arkadiusz.makarenko]

What is your DTACK term look like??

Code: Select all

);

wire rtc_decode = A[23:16] == 8'b1101_1100; //RTC registers at $DC0000 - $DCFFFF read,
wire Memory_decode = A[23:8] == {16'hB000}; 
wire JOY1DATA = A[23:3] == {20'hDFF00, 1'b1}; 


wire punt_int = rtc_decode|Memory_decode|JOY1DATA ;

reg rtc_int;
reg mem_int;
reg joy_int;
reg intsig_int;
reg punt_ok;

always @(posedge CLKCPU_A) begin 
	rtc_int <= PUNT_IN & rtc_decode ;
	punt_ok <= PUNT_IN & punt_int;
	mem_int <= PUNT_IN & Memory_decode;	
	joy_int <= PUNT_IN & JOY1DATA;	
end



always @(posedge CLKCPU_A or posedge AS20) begin 
	if (AS20 == 1'b1) begin 
		intsig_int <= 1'b1;
	end else begin 
		if (INTSIG7 == 1) begin
			intsig_int <= 1'b0;
		end else begin
			intsig_int <= 1'b1; 
		end	
	end
end 




// punt works by respecting the accelerator punt over our punt.
assign PUNT_OUT = PUNT_IN ? ( punt_int ? 1'b0 : 1'b1) : 1'b0;

assign INTSIG2 = rtc_int;
assign INTSIG8 = mem_int|joy_int;   

assign DSACK = punt_ok?{1'b1, intsig_int}:2'bzz ;


assign INTSIG3 = A[3];
assign INTSIG5 = A[5];

[terriblefire]

Only thing i can think of is that the odd part of the address is somehow getting ACK'd at the same time as the high part.

So when the CPU get the first DTACK the arm is asserting ACK when the second one arrives. So it DTACKS again with the same data.

Maybe make the CPLD have to see a transition on ACK to do the acknowledge.

[terriblefire]

Only thing i can think of is that the odd part of the address is somehow getting ACK'd at the same time as the high part.

So when the CPU get the first DTACK the arm is asserting ACK when the second one arrives. So it DTACKS again with the same data.

Maybe make the CPLD have to see a transition on ACK to do the acknowledge.

e.g.

Code: Select all

reg ack[1:0]
reg actual_acknowledge = 0;

always @(posedge CLKCPU_A) begin 
   actual_acknowledge <= ack == 2'b01;  
   ack <= {ack[0], ack_from_arm};
end 

[arkadiusz.makarenko]

Only thing i can think of is that the odd part of the address is somehow getting ACK'd at the same time as the high part.

So when the CPU get the first DTACK the arm is asserting ACK when the second one arrives. So it DTACKS again with the same data.

Maybe make the CPLD have to see a transition on ACK to do the acknowledge.

e.g.

Code: Select all

reg ack[1:0]
reg actual_acknowledge = 0;

always @(posedge CLKCPU_A) begin 
   actual_acknowledge <= ack == 2'b01;  
   ack <= {ack[0], ack_from_arm};
end 

That is exactly what the issue was, but it seems like ARM is struggling to serve interrupts that close to each other on one interrupt group(?). I will try to solve it by using different interrupt group for H and L.

PS
I will need to learn how to move program from flash to RAM at boot and execute it directly from RAM, as apparently there is noticeable cost of executing code from build in flash, which might be important for interrupts.

Edit
Maybe delaying IRQ by few cycles would help?

In above scenario would I even see transition on interrupt to ARM as one adress goes exactly to another covered by interrupt range? What I am saying is do I need to find a way of inserting low state between interrupts on adresses 0 and 1?
...

[terriblefire]

You wont get a second interrupt because the address wont return away from the value you decode.

If you AS20 in the decode term for the decode you'll get the interrupt disasserted and reasserted.

Otherwisee Address will simply increment but that wont result in a new interrupt transition.

Like i said before you should really check immediately after the first interrupt for the second address being requested since it will always be requested.

Also ensure DTACK is always triggered by a transition as per above.

[arkadiusz.makarenko]

! !

Ok Some success

I did tie up interrupt to ARM with Address strobe, so interrupt is issued only when address strobe is asserted and interrupt condition true.
Now DTACK is ticked only once, each address decoder issue one interrupt per one decoded address and ARM serves all interrupts.

Code: Select all

	if (AS20 == 1'b0) begin
		joy_int <= PUNT_IN & JOYDATA;
	end else begin 
		joy_int <= 1'b0;
		end

20201020_214613.jpg (313.84 KiB) Viewed 2253 times

Only one anomaly is that one address doesn't fully match how I understand it .
$DFF00C reads as H 0xC but L as 0xF ... but there is section on misaligned addresses in 68020 reference manual which I still need to fully understand, but there are reference about controling sections of read by using A0 and A1 this would match other register Joy0DAT where L section has A0 =1 and A1 = 1 ... I might be wrong, but at this point I don't care I want mouse or even joypad working at any cost!