EXPANSION HEADERS REV H1

[exxos]

As mentioned before, the first expansion header will be the return of the DIP 68000 socket. The board can use either a PLCC CPU or DIP CPU.

The PLCC CPU will remain as the main CPU, simply because the 68000 DIP socket is intended as a expansion header, so can be used for a 030 or IDE interface etc.

I may add a special header with the intention of a IDE interface as the DIP 68000 socket is large.

I don't think there will be a whole lot of room left on the MB after all current mods are done. Main issue is space under the keyboard for expansion headers.

[PaulJ]

As mentioned before, the first expansion header will be the return of the DIP 68000 socket. The board can use either a PLCC CPU or DIP CPU.

The PLCC CPU will remain as the main CPU, simply because the 68000 DIP socket is intended as a expansion header, so can be used for a 030 or IDE interface etc.

I may add a special header with the intention of a IDE interface as the DIP 68000 socket is large.

I don't think there will be a whole lot of room left on the MB after all current mods are done. Main issue is space under the keyboard for expansion headers.

I second this approach, I really have no use for a on board IDE interface. I'm pretty much commited to ultra satan and may even use one internally if the internal DMA connector is present. Having the 64 pin dip as a basis for different cpu boosters is a good idea. Plugging a boosters into an SMD socket in my mind is problematic and not something I'd do. I really hate doggy connections. I would consider taking a SMD booster and soldering it into an 64 pin dip adapter.

[exxos]

A thought popped into my head just..

With the addition of a GAL next to the PLCC CPU, it would in effect become the "STE booster" design. Other than routing DTACK & CLK8 via the GAL (can be jumper linked to bypass anyway) the STE booster GAL chip should pretty much "drop in".

It would give the MB a speed boost for doing pretty much nothing work wise, and takes the pressure off me a bit to finish the SEC design.

[PaulJ]

A thought popped into my head just..

With the addition of a GAL next to the PLCC CPU, it would in effect become the "STE booster" design. Other than routing DTACK & CLK8 via the GAL (can be jumper linked to bypass anyway) the STE booster GAL chip should pretty much "drop in".

It would give the MB a speed boost for doing pretty much nothing work wise, and takes the pressure off me a bit to finish the SEC design.

That sounds like a good idea to me. Since there are going to be quite a few changes and upgrades we should divide up the design and check for issues when your finished to see if we can head off any un-fu*kit boards especially in the connector area..

[IngoQ]

I vaguely remember, that the MegaBus is basically the 68000 pin out with some (more or less) simple logic added. Although I am quite sure this has been discussed already, I thought I mention it

[exxos]

I vaguely remember, that the MegaBus is basically the 68000 pin out with some (more or less) simple logic added. Although I am quite sure this has been discussed already, I thought I mention it

Yeah, the connector is way to big, it could be done as a normal pin header.. Can't remember off-hand what the differences was in the signals to the megabus adapter.

[IngoQ]

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