Current 16MHz & FPGA plotting (NEW JUMPERS LIST)
Posted: Fri Jul 12, 2019 9:11 pm
I have removed the 74F04 buffer chip and have started breaking up the clock lines with the intention of creating a new 16MHz mod board which will plug into the H2.
Basically there will be a row of jumpers which will basically replace all the jumper wire problems as we have with 16MHz on the Alpha.. So the stock machine can be set with one combination of jumpers, and then the jumpers can be removed, and it doubles up as a expansion header where the 16 MHz mod board plugs into.
As mentioned in the other thread a little ... https://www.exxosforum.co.uk/forum/viewt ... =50#p24031 I was in two minds if to start doing this or not.. As all these jumpers basically makes things a lot more complicated... And as said as well, integrating the 16MHz board would actually be a bit of a disaster for when the FPGA stuff comes into play, As it will basically be in the way and have to be removed..
But the point is, the FPGA board will be generating the clocks, so it has to plug into some connector somewhere on the motherboard anyway... So basically the jumper links will double up as the 16MHz & FPGA "clock generator connector". Then theoretically we should be pretty future proof when we start accelerating things more.
The image above is not complete with all jumpers yet, it is still WIP...
Basically there will be a row of jumpers which will basically replace all the jumper wire problems as we have with 16MHz on the Alpha.. So the stock machine can be set with one combination of jumpers, and then the jumpers can be removed, and it doubles up as a expansion header where the 16 MHz mod board plugs into.
As mentioned in the other thread a little ... https://www.exxosforum.co.uk/forum/viewt ... =50#p24031 I was in two minds if to start doing this or not.. As all these jumpers basically makes things a lot more complicated... And as said as well, integrating the 16MHz board would actually be a bit of a disaster for when the FPGA stuff comes into play, As it will basically be in the way and have to be removed..
But the point is, the FPGA board will be generating the clocks, so it has to plug into some connector somewhere on the motherboard anyway... So basically the jumper links will double up as the 16MHz & FPGA "clock generator connector". Then theoretically we should be pretty future proof when we start accelerating things more.
The image above is not complete with all jumpers yet, it is still WIP...