Clock generator for TF360 rev 1

News & updates for the upcoming 68060 accelerator

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terriblefire
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Re: Clock generator for TF360 rev 1

Post by terriblefire » Tue Sep 10, 2019 8:31 pm

It would port over to any machine that implemented some kind of NVRAM and exposed it as a nonvolatile.library... which i think would be the best way to do nvram on any machine..

But yes. No other machine has that yet.
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richx
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Re: Clock generator for TF360 rev 1

Post by richx » Sat Sep 14, 2019 4:56 pm

Software controlled clock sounds great. To prevent runaway code looping all memory and setting unexpected frequencies, two registers could be used in sequence, or being able to optionally lock further settings until reset would also prevent (to a degree) any rogue program from misbehaving.

Having said that, would it still be worth to leave PCB space for a couple of GPIOs exposed from CPLD (can CPLD pins be configured with pullups/pulldowns) for future use? Could be used to disable the 64k autoconfig device, force 50MHz for non-boots, disable on-board IDE etc.

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Re: Clock generator for TF360 rev 1

Post by terriblefire » Sat Sep 14, 2019 5:00 pm

richx wrote:
Sat Sep 14, 2019 4:56 pm
Software controlled clock sounds great. To prevent runaway code looping all memory and setting unexpected frequencies, two registers could be used in sequence, or being able to optionally lock further settings until reset would also prevent (to a degree) any rogue program from misbehaving.
Possibly. Although im not letting this get set raw. Its an allowed list of frequencies selected from a table.
Having said that, would it still be worth to leave PCB space for a couple of GPIOs exposed from CPLD (can CPLD pins be configured with pullups/pulldowns) for future use? Could be used to disable the 64k autoconfig device, force 50MHz for non-boots, disable on-board IDE etc.
Nah... there arent any free pins. All 288 pins are in used on this board. i've had to be cruel and creative to get this to fit as it is.
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Re: Clock generator for TF360 rev 1

Post by terriblefire » Sat Sep 14, 2019 5:14 pm

OK so the rev 1 is done and i've chosen this chip for the clockgen...

https://uk.rs-online.com/web/p/pll-freq ... s/1628970/

Reasons are that its relatively simple, small footprint and cheap ish. It gives good multilpy options in the range we want.

The firmware will not let you hit these pins directly they'll be chosen from a table. The onboard crystal will be a the same SMD form factor crystal but at 25Mhz.

The output frequencies you can select will be
Multiplier RAMCLK CPUCLK
3.7593.7546.875
410050
512562.5
615075
6.25156.2578.125
6.333158.32579.1625
8200100
8.3333208.3325104.16625
I'll also allow a straight 14Mhz option.

There is a jumper to disable the 060 and onboards.

I've dramatically beefed up the decoupling in critical areas. Not sure how much this is needed but it wont hurt.

I'm going to recommend a -7 RAMCPLD if you want to get to 100Mhz. I think we're basically hitting the CPLD limits now.
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