Programming the CPLD

68030 + SDRAM + IDE

Moderators: terriblefire, Terriblefire Moderator

Scrappysphinx
Posts: 17
Joined: Wed May 25, 2022 7:48 am

Programming the CPLD

Post by Scrappysphinx »

Hi all, i bought a TF536 pcb from the exxos store here which arrived yesterday. I got the CPLD and other parts from Supaduper and assembled it all last night. I have now come to programming and i have grabbed Supaduper's image along with a pi 3b. I have connected the jtag points according to the attached picture. I have tried using the 3.3v from the pi to power it but get a "No JTAG Chain Found" error when trying to program.

I then tried plugging the board into an amiga to provide power but get the same error again.

I have reflowed the CPLD a number of times (pic of soldering attached) but i just can't get it to program.

I was using Dupont cables but have also tried soldering wires directly to the pi and tf536 but same error every time

I have a pi zero 2 i was going to try in case its my pi 3 but Mark's image doesn't seem to boot on the Zero 2

Any tips would be appreciated :)

gpio.png
gpio.png (54.58 KiB) Viewed 2164 times
cpld.jpg
cpld.jpg (193.29 KiB) Viewed 2164 times
go0se
Posts: 404
Joined: Sun Nov 25, 2018 7:55 pm

Re: Programming the CPLD

Post by go0se »

When you power the card from the Amiga, and without the Pi connected check that you have a stable 3.3V by measuring between the labelled 3.3V and GND pads on the JTAG header of the 536.

If you don't get a stable 3.3V approx, then there is a short somewhere. First suspect is always the CPLD, then the memory chips, then the level shifters. Keep in mind that even if the soldering on the CPLD looks good there can still be a short behind the pins, in which case it will need to be lifted and refitted.

Add some top down and 45 degree angle pics of the memory chips and the level shifters. Your photo also only shows 2/4 sides of the CPLD, which look good to me.

I am unfamiliar with the Pi GPIO layout so perhaps someone else could confirm that what you are using is correct for the model of Pi that you are using.
Scrappysphinx
Posts: 17
Joined: Wed May 25, 2022 7:48 am

Re: Programming the CPLD

Post by Scrappysphinx »

I get 3.3v when measuring the ground and 3.3v of the JTAG connection.

I've attached pics of the cpld from above and all sides along with the ram and registers. The circled area of ram looks like a short but I think it's just the silkscreen through the legs. I tested it with the multimeter and there is no bridge there.

I'm not sure if it makes a difference or not but I'm powering it in a 600 with a plcc to dip adapter from Lemaru cause my 500++ board it will be used in is away being checked over by Peter Mulholland

IMG_20220528_182815.jpg
IMG_20220528_182815.jpg (299.03 KiB) Viewed 2132 times
IMG_20220528_182742.jpg
IMG_20220528_182742.jpg (311.46 KiB) Viewed 2132 times
IMG_20220528_182615.jpg
IMG_20220528_182615.jpg (312.37 KiB) Viewed 2132 times
IMG_20220528_182519.jpg
IMG_20220528_182519.jpg (336.61 KiB) Viewed 2132 times
IMG_20220528_182503.jpg
IMG_20220528_182503.jpg (292.38 KiB) Viewed 2132 times
IMG_20220528_182449.jpg
IMG_20220528_182449.jpg (263.9 KiB) Viewed 2132 times
IMG_20220528_182437.jpg
IMG_20220528_182437.jpg (258.97 KiB) Viewed 2132 times
IMG_20220528_182428.jpg
IMG_20220528_182428.jpg (268.94 KiB) Viewed 2132 times
IMG_20220528_182411.jpg
IMG_20220528_182411.jpg (448.13 KiB) Viewed 2132 times
go0se
Posts: 404
Joined: Sun Nov 25, 2018 7:55 pm

Re: Programming the CPLD

Post by go0se »

Shifters.jpg
Shifters.jpg (341.95 KiB) Viewed 2109 times


The circled area on the the left looks like it is probably cloth fluff but the circled area on the right is slightly more suspicious. There is also a possible short on the level shifter on the far right underneath pin 1 (not circled in the image)

Test the JTAG TDI,TDO,TCK and TMS pins for continuity with the CPLD. The easiest way to locate the pins is to place one probe on the corresponding JTAG header pin and then strafe all the pins on the CPLD with the other. Then check that your pin location corresponds to the datasheet.

Screenshot from 2022-05-28 21-03-18.png
Screenshot from 2022-05-28 21-03-18.png (35.16 KiB) Viewed 2109 times

The CPLD *should* still program if it is receiving 3.3V and the JTAG connections are sound, even if address/data lines are shorted elsewhere.

That makes me think that your Pi setup is possibly to blame.
Scrappysphinx
Posts: 17
Joined: Wed May 25, 2022 7:48 am

Re: Programming the CPLD

Post by Scrappysphinx »

So checked the registers and definitely no bridges.

Checked the JTAG header to the cpld which has continuity so may well be my pi.

I'll have to see if I can get an os and the programming software installed on my zero 2 and see if I have any success with that

IMG_20220528_213342.jpg
IMG_20220528_213342.jpg (267.01 KiB) Viewed 2090 times
IMG_20220528_213333.jpg
IMG_20220528_213333.jpg (268.2 KiB) Viewed 2090 times
Scrappysphinx
Posts: 17
Joined: Wed May 25, 2022 7:48 am

Re: Programming the CPLD

Post by Scrappysphinx »

Hi again, I'm at a loss here so any more help would be appreciated :)

so i borrowed a xilinx jtag programmer from a friend which looks like this

xilinx3.jpg
xilinx3.jpg (42.75 KiB) Viewed 2004 times

I have installed ISE 14.7 from the xilinx website along with Oracle Virtual Box

Opening impact and allowing boundary scan detects the cpld and i can select the jed file but i don't have any options regarding blank cheks/erase/programming.

xilinx1.png
xilinx1.png (173.52 KiB) Viewed 2004 times
xilinx2.png
xilinx2.png (156.21 KiB) Viewed 2004 times
terriblefire
Moderator Team
Moderator Team
Posts: 5388
Joined: Mon Aug 28, 2017 10:56 pm
Location: Glasgow, UK

Re: Programming the CPLD

Post by terriblefire »

Already mentioned this many times on the forum. You need to reset the cable between each operation with those clones.
———
"It is not necessarily a supply voltage at no load, but the amount of current it can provide when touched that
indicates how much hurting you shall receive."
User avatar
stephen_usher
Posts: 5660
Joined: Mon Nov 13, 2017 7:19 pm
Location: Oxford, UK.
Contact:

Re: Programming the CPLD

Post by stephen_usher »

I've found the WaveShare ones to be fine, but they don't try to pretend to be Xilinx units, although they look the same.

The WaveShare customer support was good too. When I did have a problem the first thing they did was to ship a new, pre-tested unit next day with free shipping back for the original unit and then went through a proper diagnosis via e-mail. I can't fault ihem.
Intro retro computers since before they were retro...
ZX81->Spectrum->Memotech MTX->Sinclair QL->520STM->BBC Micro->TT030->PCs & Sun Workstations.
Added code to the MiNT kernel (still there the last time I checked) + put together MiNTOS.
Collection now with added Macs, Amigas, Suns and Acorns.
Scrappysphinx
Posts: 17
Joined: Wed May 25, 2022 7:48 am

Re: Programming the CPLD

Post by Scrappysphinx »

Thanks for the reply, after multiple cable resets i finally got some options, i have programmed it with the r2 jed file, reset the cable but verify fails :(

After another few resets i can erase, reset, program, verify fails.

Rinse and repeat sadly
User avatar
supaduper
Posts: 566
Joined: Thu Nov 08, 2018 12:05 pm

Re: Programming the CPLD

Post by supaduper »

Also try Erasing the CPLD before programming this can help sometimes
Post Reply

Return to “TF536”