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TOS startup sequence.

Posted: Mon Sep 17, 2018 10:26 pm
by exxos
Trying to find more info on this.. only found this so far...

System_Startup.jpg
System_Startup.jpg (462.26 KiB) Viewed 3062 times

https://info-coach.fr/atari/documents/_ ... tartup.jpg

Re: TOS startup sequence.

Posted: Mon Sep 17, 2018 10:33 pm
by troed
That's pretty much what needs to be known.

startup.S in the re-created TOS 2.06/3.06 source code package is where this can be read in assembly code.

Re: TOS startup sequence.

Posted: Mon Sep 17, 2018 11:05 pm
by exxos
It sparked my interest as if 50Hz is being set, but not the palette data (still black screen) what actually goes on in the code between those 2 things ?

Re: TOS startup sequence.

Posted: Tue Sep 18, 2018 8:00 am
by Petari
Actually, initial palette is set right after Vfreq. set, so nothing happens between those 2 :D Checked in TOS 1.04 and 2.06 .
It is all in very early stage, so many things will be set after it, before first screen output.

Re: TOS startup sequence.

Posted: Tue Sep 18, 2018 1:37 pm
by exxos
Can someone post the source file here ? Would be even better if someone could maybe label up exactly what is going on in the startup code step by step.

Re: TOS startup sequence.

Posted: Tue Sep 18, 2018 2:19 pm
by troed
exxos wrote:
Tue Sep 18, 2018 1:37 pm
Can someone post the source file here ? Would be even better if someone could maybe label up exactly what is going on in the startup code step by step.
Yeah I had that thought yesterday when looking through it, just need to manually remove all ifdef:ed code only valid for TT/Falcon.

Re: TOS startup sequence.

Posted: Tue Sep 18, 2018 3:07 pm
by Petari
Here is begin of TOS 1.04 (ST) , with some comments .
TOS104SU.ZIP
(4.59 KiB) Downloaded 123 times
Can add more comments, just need some time and what is exactly of interest.
It's not hard to follow once you get used on strange HW addressing at most places:

Code: Select all

	suba.l	a5,a5
	lea	-$7800(a5),a0
	move.b	#7,(a0)
	move.b	#$C0,2(a0)
	move.b	#$E,(a0)
	move.b	#7,2(a0)
Above is PSG initialisation. -$7800 is same as $FFFF8800.w

Re: TOS startup sequence.

Posted: Tue Sep 18, 2018 3:15 pm
by exxos
Thanks.. it is confusing the address, could you add in what the proper address is plus what chip it is actually accessing ?

Re: TOS startup sequence.

Posted: Tue Sep 18, 2018 6:54 pm
by Petari
It's simple in fact. Negative value is 16-bit, and if you sub it from $10000 will get 16-bit positive value - what is in case of HW port always negative number (bit 15 is 1). You can use Windows calculator in programmer and hex mode for it.
-$7FFF = $10000-$7FFF = $8001 - MMU config reg. Physical address is of course, because bit 15 is copied to bits 16-31 (sign extension) : $FF8001
-$7800 = $10000-$7800 = $FF8800 PSG base
-$7DF6 = $10000-$7DF6 = $FF820A Vfreq
-$7DC0 = $10000-$7DC0 = $FF8240 Palette
-$7DFF = $10000-$7DFF = $FF8201 Video base high
-$7DFD = $10000-$7DFD = $FF8203 Video base mid
Writing in above 2 1 and 0 sets screen to $10000 .
So much for now.

Re: TOS startup sequence.

Posted: Tue Sep 18, 2018 7:14 pm
by troed
Alright, here's a cleaned up (TOS 3.x/4.x/STBOOK stuff etc removed - I hope I got the sections right) startup.S from the TOS source code package:

Code: Select all


_main:
/* disable the interrupts */
/* this is useless on cold boot, */
/* but it matters for software reset */
        move    #$2700,sr

        reset                  /* reset all hardware */

/*
 * Check for diagnostic cartridge
 */
        cmp.l   #$fa52235f,cart_base    /* magic - is cartridge present? */
        bne.s   nodiag                  /* no -> go on */
        lea     nodiag(pc),a6           /* save return address */
        jmp     cart_base+4             /* execute diagnostig cartridge */
nodiag:

        lea       memcret(pc),a6
        bra       memchk
memcret:
        bne.s      noreset
        move.b    (memctrl).w,(memconf).w  /* initialize memory controller */

resetvec:
/*
 * Check, if we should jump to a reset vector after warmboot
 * The high byte of resvector must be zero,
 * it must be even, and cannot be entirely zero.
 */


        cmpi.l   #$31415926,(resvalid).w  /* Jump to resetvector? */
        bne.s    noreset                /* No --> noreset */
        move.l   (resvector).w,d0       /* Yes: old resvec to d0 */
        tst.b    (resvector).w          /* bits 24..31 must be zero */
        bne.s    noreset                /* (they aren't, so punt) */
        btst     #0,d0                  /* Address odd ? */
        bne.s    noreset                /* Yes --> noreset */
        movea.l  d0,a0                  /* resvec */
        lea      resetvec(pc),a6        /* save return address */
/* Note: the return address intentionally points to the resvalid test. */
/* So the reset routine must explicitly clear resvalid before returning */
/* to a6, otherwise there will be an infinite loop. */
        jmp      (a0)                   /* jump to resvec */
noreset:


/*
 * memory configuration
 */

/*
 * do/test memory config and clear it
 *  Initialize PSG output ports.
 *  Make port A and B output-only,
 *  initialize floppy select lines (so
 *  that none are selected)
 */
meminit:

        lea.l     (psgsel).w,a0
        move.b    #$07,(a0)  /* select mixer control */
        move.b    #$C0,2(a0) /* Port A+B = output */
        move.b    #$0E,(a0)  /* select Port A */
        move.b    #$07,2(a0) /* deselect floppy drives */

        btst      #0,_os_conf+1             /* check bit: configured for 50hz? */
        beq.s     notpal                    /* (nope -- we're good ol' NTSC) */
        lea       ret_1b(pc),a6
        bra       waitvbl                   /* a short delay for PAL */
ret_1b: move.b    #2,(v_syncmod).w          /* yes -- twiddle to 50hz */
notpal:

/*
 * next, set up the palette(s)
 */

        lea.l     (palette).w,a1
        move.w    #16-1,d0
        lea.l     dflt_pal(pc),a0
initpal:
        move.w    (a0)+,(a1)+
        dbf       d0,initpal

/* set Video screen memory position to 0x10000 */
        move.b    #$01,(v_bas_h).w
        clr.b     (v_bas_m).w

        move.b    (memctrl).w,d6                /* d6 = memory controller configuration */
        move.b    d6,(memconf).w                /* setup memory controller configuration register */

        move.l    (_phystop).w,d5               /* d5 -> (possible) top of physical mem */
        lea       memcret2(pc),a6               /* load return address */
        bra       memchk                        /* check if the memory configuration is valid */
memcret2:
        beq       nomemchk

/* First we try to configure the memory controller */

            clr.w     d6
            move.b    #$a,(memconf).w			/* default: setup controller for 2Mb/2Mb */

            movea.w   #$8,a0
            lea       $200008,a1				/* + 2Mb */
            clr.w     d0
chkpatloop: move.w    d0,(a0)+					/* fill 512-8 bytes with a test pattern */
            move.w    d0,(a1)+
            add.w     #$fa54,d0
            cmpa.w    #$200,a0
            bne.s     chkpatloop

            move.b    #90,(v_bas_l).w			/* wrote low byte of video address */
            tst.b     (v_bas_m).w				/* touch the middle byte (this should reset the low byte) */
            move.b    (v_bas_l).w,d0
            cmp.b     #90,d0					/* low byte not reset? */
            bne.s     chkmem1
            clr.b     (v_bas_l).w				/* try a different low byte value */
            tst.w     (palette).w				/* touch the color palette */
            tst.b     (v_bas_l).w				/* low byte changed? */
            bne.s     chkmem1
            move.l    #$40000,d7				/* 256Kb offset */
            bra.s     chkmem1b
chkmem1:    move.l    #$200,d7					/* 512 byte offset */
chkmem1b:   move.l    #$200000,d1				/* 2Mb = maximum size per bank */

chkmemloop: lsr.w     #2,d6						/* shift memory configuration down by a bank (bank 1 is in bits 0..1, bank 0 is in bits 2..3) */

            movea.l   d7,a0						/* + 512/256Kb bytes */
            addq.l    #8,a0
            lea       chkmem3(pc),a4
            bra       memchk0
chkmem3:    beq.s     chkmem7					/* bank is not working => */

            movea.l   d7,a0
            adda.l    d7,a0						/* + 1024/512Kb byte */
            addq.l    #8,a0
            lea       chkmem4(pc),a4
            bra       memchk0
chkmem4:    beq.s     chkmem6					/* bank has 512Kb of memory => */

            movea.w   #$8,a0					/* + 0 bytes */
            lea       chkmem5(pc),a4
            bra       memchk0
chkmem5:    bne.s     chkmem7					/* bank is empty => */

            addq.w    #4,d6						/* 4+4 = 1000 2Mb bank size */
chkmem6:    addq.w    #4,d6						/* 4   = 0100 512Kb bank size */
chkmem7:    sub.l     #$200000,d1				/* - 2Mb */
            beq.s     chkmemloop
            move.b    d6,(memconf).w			/* set memory configuration */

/* =========================================================================== */
/* ==== This part is executed only on first boot ============================= */
/* =========================================================================== */

        /* Clear the memory */
        movea.w   #sysvars_start,a0
        move.l    d5,d4
        moveq.l   #0,d0
clrmem:
        move.l    d0,(a0)+
        move.l    d0,(a0)+
        move.l    d0,(a0)+
        move.l    d0,(a0)+
        cmpa.l    d4,a0
        bne.s     clrmem

        /* Store the ST-RAM parameters in the ST-RAM itself */
        move.b  d6,(memctrl).w             /* set copy of hw memory config */

        move.l  d5,(_phystop).w            /* highest address as phystop */

        move.l    #$752019F3,(_memvalid).w /* set memvalid to ok */
        move.l    #$237698AA,(_memval2).w  /* set memval2 to ok */
        move.l    #$5555AAAA,(_memval3).w  /* set memval3 to ok */
... after this comes fastram init, STE DMA sound init etc. This represents the code behind steps 1-7 in the flow chart above.