exxos's Atari, Amiga & retro forum

Close enough?

Yeah, I'd like to see what someone else gets on these datalines in reset.

EDIT: Since it was handy, I swapped in a different 68000 IC. No change.

Have you tried to boot the diagnostic cart ?

exxos wrote: ↑Mon Dec 02, 2019 1:27 pm Have you tried to boot the diagnostic cart ?

Sure have. Nothing on serial, with a setup confirmed to work when booting it in a real ST. With or without the diagnostic cart, BERR is dropping low frequently. I have not yet looked really closely at logic analysis output to see if it's doing anything differently with and without the diag cart, but that's on my list of things to do. Also I'm going to look at decoding the whole bus on a working ST and on the H4 to see whether I can see it trying to load TOS at all. (Bear in mind of course that I do not really know what I'm doing here, and I'm learning this stuff as I go, so my efforts are far from expert diagnostic work.)

By the way, what should happen (all other things being functional that is) if an 8 MB SIMM is used in the SIMM slot? I don't have any 4 MB 72-pin SIMMs, and although this 4 MB Falcon RAM board is known good, it's good to have additional diagnostic options if possible.

I wired the simms other address lines to gnd, so using a 8MB or 16MB should be fine.

I think you need to monitor the first bus cycle, you need to confirm you have all zero's on the bus when /AS goes low for the first time (along with ROM_CE). Thats the CPU's first instruction fetch from ROM. If the address is wrong, it could try to run instructions from a random point in ROM and then CPU crashes. Troed listed the first assembly instructions on what happens when, but I don't much about asm.

CLOCKS

These are some pictures of all the clocks, which I hope/think are all good. Hopefully these are useful to others knowing what they're looking for when going through their own troubleshooting procedures.

CPU 8 MHz CLK (PLCC pin 15)

MMU 16 MHz CLK (PLCC pin 5)

MMU 4 MHz out (PLCC pin 19)

MMU 8 MHz out (PLCC pin 20)

GLUE 8 MHz CLK (PLCC pin 34)

GLUE 500 kHz out (PLCC pin 43)

GLUE 2 MHz out (PLCC pin 54)

MFP 4 MHz CLK (pin 35)

WD1772 8 MHz CLK (pin 18)

BAD DMA 8 MHz CLK (pin 39)

ACIA 500 kHz CLK (pins 3, 4)

exxos wrote: ↑Mon Dec 02, 2019 2:26 pm I think you need to monitor the first bus cycle, you need to confirm you have all zero's on the bus when /AS goes low for the first time (along with ROM_CE). Thats the CPU's first instruction fetch from ROM.

Yep, that's the next thing on my list.

Okay, so here's just over half the bus on a reset (16 channel limit on my analyser, will do the rest momentarily)...

My RESET does that double-flip thing every time. Is that normal? There is no mention in the troubleshooting guide of expecting it to go up, down, up again. But it's totally consistent behaviour in my H4.

Which brings up the second interesting thing. At least amongst A1-A13, they indeed do all drop to 0 at the same time as AS does, but only on the first reset rise. On the second reset rise, A3-5 do not drop until several cycles later.

Will now go hook up the rest of the bus and run it again.

And here's the rest of the bus, as well as ROM_CE and DTACK. Similar behaviour.

EDIT: Added DTACK.

I have seen that behavior before , I thought it was down to the iffy 555 reset circuit..I no idea if that's normal for tos or not though.

There seems a lot of bus activity, does the floppy light come on on the keyboard ?

derkom wrote: ↑Mon Dec 02, 2019 3:37 pm And here's the rest of the bus, as well as ROM_CE and DTACK. Similar behaviour.

EDIT: Added DTACK.

What happens after the image you posted ? Does it die totally later ?