Project: HDMI/DVI out for STFM

Progress on our FPGA cores.
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exxos
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Re: Project: HDMI/DVI out for STFM

Post by exxos » Fri Aug 31, 2018 11:27 am

Smonson wrote:
Fri Aug 31, 2018 10:54 am
No worries! I hope it's nothing serious, my track record so far isn't looking good otherwise :lol:
Welcome to the world of Atari :lol:
Smonson wrote:
Fri Aug 31, 2018 10:54 am
You can also read vsync off the following 3 pins arrowed in blue.
Cool.. will do that as well...
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Re: Project: HDMI/DVI out for STFM

Post by exxos » Fri Aug 31, 2018 6:39 pm

IMG_3248.JPG
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Re: Project: HDMI/DVI out for STFM

Post by exxos » Fri Aug 31, 2018 7:03 pm

My first finding is noise somewhere... "finger on board" solves it...





Looks like U2 is a 16Mz buffer.. has really bad ringing on it.. with my finger on it, the image jumps to the left a couple of pixels and is stable.. without finger.. jumps to the right and has the odd horizontal noise lines shown in my video..

I suspect the buffer simply needs something like 100R on its input and output stop the ringing.. And would assume the picture would be rocksolid stable then...

Otherwise, seriously impressive stuff!
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Re: Project: HDMI/DVI out for STFM

Post by troed » Fri Aug 31, 2018 7:07 pm

Great!

And no spontaneous resets I guess?

(I don't have the finger-on-board need as far as I've seen. Haven't run medium res at all though I think)

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Re: Project: HDMI/DVI out for STFM

Post by exxos » Fri Aug 31, 2018 7:13 pm

troed wrote:
Fri Aug 31, 2018 7:07 pm
And no spontaneous resets I guess?
Not yet.. Not been running very long anyway..

Though if you're getting odd resets, it is likely noise on the 16Mhz line I assume...
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Re: Project: HDMI/DVI out for STFM

Post by exxos » Fri Aug 31, 2018 7:20 pm

This is a bad fix..

But it solves my problem.. Where ever that 16MHz is going (middle right pin of U2) it needs 100R in there..

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Re: Project: HDMI/DVI out for STFM

Post by troed » Fri Aug 31, 2018 7:25 pm

Hmm. So that's on the output from the 16MHz generated by the FPGA, before it ends up at the Shifter socket clk_out pin (from where it goes to the MMU, and then becomes all other clocks).

Unfortunately does not help me. I'm not using clocks from the FPGA - I clock _it_ from my GAL (and the GAL also clocks everything else). So my resets are caused by something else.

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Re: Project: HDMI/DVI out for STFM

Post by exxos » Fri Aug 31, 2018 7:36 pm

troed wrote:
Fri Aug 31, 2018 7:25 pm
I clock _it_ from my GAL (and the GAL also clocks everything else). So my resets are caused by something else.
Probably one of those times just to put your scope on all the clock pins one by one.. if it crashes when you touch one clock, then that signal is over sensitive.. Loading of the scope can also help clean up noise on clocks.. so scope on one line may solve the problem.. assuming its clock noise that is.
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Re: Project: HDMI/DVI out for STFM

Post by troed » Fri Aug 31, 2018 7:44 pm

exxos wrote:
Fri Aug 31, 2018 7:36 pm
Probably one of those times just to put your scope on all the clock pins one by one.. if it crashes when you touch one clock, then that signal is over sensitive.. Loading of the scope can also help clean up noise on clocks.. so scope on one line may solve the problem.. assuming its clock noise that is.
Well, it's rock solid with the original Shifter - so it's at least something that somehow gets affected by the FPGA. But I also have resets (less often) using only the FPGA exactly like you are, without my GAL.

Smonson and I have debated whether there could be a fault on mine and so we've been waiting for you to run yours ... :) But I'm sure it's something fixable. I just don't know what causes it yet.

(and I'm off for another week in the US next week so will likely not have an answer for a while)

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Re: Project: HDMI/DVI out for STFM

Post by exxos » Fri Aug 31, 2018 7:52 pm

troed wrote:
Fri Aug 31, 2018 7:44 pm
Well, it's rock solid with the original Shifter - so it's at least something that somehow gets affected by the FPGA. But I also have resets (less often) using only the FPGA exactly like you are, without my GAL.
Does anything change with the clocks at all from the shifter being inserted to the FPGA board ? Does any clock lines get different loads between shifter vs FPGA ( I don't really know how its all hooked up in your machine or how the FPGA clocks are working )
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