If we disregard it happening on my doubleST where no, the FPGA cannot affect my clocks, then yes - replacing the Shifter with the FPGA might indeed change a lot regarding the 16MHz clock to the MMU (from which all other clocks are derived). However, I don't think I have resets due to that on my 520ST and resets (more often) due to a completely different issue on my doubleST.
So ... I'll just LA the crap out of everything and maybe scope VCC etc when the resets happen to see if I can get a clue. I think it's pretty weird. It's really an instant reset and RESET does trigger when measured on the CPU.
In the stock FPGA version it has its own 32.000MHz oscillator (so yes, you can now check demo compatibility ) and it outputs 16MHz to the MMU just as a regular Shifter. For my doubleST uses we've changed so that I provide the 32MHz clock to the FPGA (and have removed its oscillator) from my GAL.
(I'll keep further doubleST-only comments in my thread on the subject to not confuse readers who only want to know about the FPGA-as-is