exxos's Atari, Amiga & retro forum

A little overkill, but maybe this guy...
http://www.ti.com/lit/ds/symlink/cdc208.pdf


I think you could coerce some of the IDT fanouts to work as well.

Smonson wrote: ↑Mon Sep 03, 2018 1:15 am Suggestions are welcome. But from the datasheet it looks like this device is only guaranteeing to produce a 2.4v high. Dunno if the Atari would be too happy with that.

https://www.idt.com/document/dst/qs32x2245-datasheet

Datasheet a little unclear, but it lists "pass voltage" as 4V for 5V VCC.

Where did you read 2.4v ? That doesn't sound right.

exxos wrote: ↑Mon Sep 03, 2018 8:12 am https://www.idt.com/document/dst/qs32x2245-datasheet

Datasheet a little unclear, but it lists "pass voltage" as 4V for 5V VCC.

Where did you read 2.4v ? That doesn't sound right.

You've got a different datasheet there, I was talking about the NB3N551 - but I just checked again and VOH is given twice, once at 35mA where it's min. 2.4v and then again a bit further down where it's min VDD - 0.4v at 12mA, so that's a bit more like it.

I like the smallness of that one. A downside of the otherwise excellent CDC208 mentioned by Poobah is that it's really big compared to the 2x3mm chip I've got on there now.

I was thinking more about using it to buffer the 32MHz from the ST to the FPGA so that the frequency can be exact and work for the demo stuff.
I have put one of this on the new rev of our 68020 board (still not assembled one of the new one) but haven't tested it.
I think the actual Hi level is VDD – 0.4. I'm not sure what the 2.4V represents in the datasheet.

rpineau wrote: ↑Mon Sep 03, 2018 8:30 am I was thinking more about using it to buffer the 32MHz from the ST to the FPGA so that the frequency can be exact and work for the demo stuff.
I have put one of this on the new rev of our 68020 board (still not assembled one of the new one) but haven't tested it.
I think the actual Hi level is VDD – 0.4. I'm not sure what the 2.4V represents in the datasheet.

It's probably just being pulled down by the high current, 35mA must be near the maximum it's intended to supply.

Unfortunately the FPGA on my shifter board is running at 3.3v, so this particular device wouldn't be able to act as a level converter in that direction (max input voltage is 3.8v when running on 3.3v supply). Maybe a resistor divider would work to reduce the voltage?

...or maybe the 32MHz clock could just be running at 3.3v in the first place, by transplanting the crystal?

Smonson wrote: ↑Mon Sep 03, 2018 10:17 am ...or maybe the 32MHz clock could just be running at 3.3v in the first place, by transplanting the crystal?

Run it through a spare lane on your level shifters.

Yeah but I thought the whole point was to use a proper clock driver

Now I found some 32.084988MHz oscs.. the bottom pcb has loads of room ?, so if enough room for a "DIP 14" osc then just bung one of those in your board.. then its the best frequency to use on all machines... but of course these are 5V... I suppose its either run it via the buffer, or they *might* run on 3.3V.. would have to check when they arrive...

Worth a try. If the osc packages aren't too big then I can always put one in the cut-out area, since it's optional.