BLITTER RE-CREATION THOUGHTS

Progress on our FPGA cores.
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Re: BLITTER RE-CREATION THOUGHTS

Post by exxos » Tue Oct 30, 2018 2:33 pm

Been talking to Wolfgang.. last email says..
i think that one bus enable is not enough. On the one hand you need a data enable which controls the tri state condition during read write operations of the blitter. On the other hand you need further enables to control the tri state condition, when the blitter is in it's idle state or when bs arbitration is in progress.
By the sounds of it, its just going to be a ongoing epic to start patching the cores to work with buffers.. While it may ultimately be a more elegant solution, I think development time and waiting for wolfgang to patch cores (he says hes not much time for this already) I think the best of the bad options is to go with seperate mosfets.. Its not going to look pretty, but its going to get the job done with minimal fuss.
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Re: BLITTER RE-CREATION THOUGHTS

Post by exxos » Sun Nov 04, 2018 11:25 am

I've been looking around for other chips and doesn't really seem much out there. As the mosfet only board is the only thing which works right, I was looking for mosfet arrays. Only low power stuff I could really find is dual mosfet packages. Though most of those seem to common pins between mosfets so they are not totally isolated from each other, so basically useless for this project. Problem here is, I am getting sidetracked with problems which I shouldn't have in the first place.

I did find some dual fets in sot23-6, and the price each is like 10p, not much, but if for example I need like 30 of them, thats £3 just in fets. Which doesn't seem much, but if I were to get 100 of these things made, thats £300 just on fets alone!

Single mosfets are way cheaper, can get them down to like 1p each.. 60 of them, 60p per board, or £60 for 100 boards in fets.

Thinking about the IC's, I think they were like £1.50 each or something like that, so while they are small , they are not really a cost effective "buy".

The boards will unfortunately be like 1cm larger than the PLCC package, and may even need 4 layer boards, and assembly costs will be likely higher because of more parts, but if these were done in bulk of 100pcbs, Its still going to work out a lot cheaper than using IC's.

Hopefully I can get something functional to get this project moving along then. Another good point is won't need any mods doing to the suska code, so that will likely speed up things by some months long term as well. Important thing is to get something functional working without spending a fortune on time or money wise. If a better solution comes up in the future, then of course design can be updated.

So I need to design a new PCB, should be simple enough. Really its just a sot23-3 package and a SMT resistor (maybe have to go down to 0603 for this) per IO pin..When I get time...
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Re: BLITTER RE-CREATION THOUGHTS

Post by ijor » Mon Dec 17, 2018 1:38 pm

Attached is a modified Suska top VHDL file to work with bidirectional buffers.

There are three direction control signals. One for the data bus, other for the address bus, and a third one for the bus control signals.

Currently the polarity is such that a high level indicates that the FPGA is driving the signal and then the bidirectional buffer should be configured from the FPGA to the system. This could be easily reversed if it happens to be more convenient for any reason.

There are three open drain signals that still need to be considered. DTACK and BGACK are open drain bidirectional signals. It is possible to implement the same mechanism as with the the other bidir signals. But in this case each signal requires its own direction control and it might be overkill. So for these two signals it might be better to use some of the directionless level shifter solutions. But it is not big deal to implement direction control at the FPGA if you still want so.

BR is an open drain output only. One possibility is to use just a simple open collector buffer. If so I should better change the signal at the FPGA to be push pull (not open drain). But here a passive solution might be better. May be just a resistor to reduce the pullup voltage at the FPGA pin?

Note that the modification is basically untested. All I did is to export the signals that were already available internally and connect them to external FPGA pins.

Also note that when using a FPGA, as opposed to a CPLD, it takes some time to load the configuration at power up time. Until then the FPGA doesn't drive any output because it doesn't know which pins are output yet. This have to be taken into consideration.
Attachments
SuskaBlitter-WithExternalBidirControl.zip
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Re: BLITTER RE-CREATION THOUGHTS

Post by exxos » Mon Dec 17, 2018 3:10 pm

:thanksyellow:

For things like DTACK, I may use a single open collector buffer.. they normally good for 30V pull down voltages. So that would solve that problem without needing anything "fancy" doing.

I am not sure when I will get chance to look into this project , hopefully in the next couple of weeks I will be caught up on other things that I can spend more time on it.

But thanks for doing the patches so quickly!
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Re: BLITTER RE-CREATION THOUGHTS

Post by ijor » Tue Dec 18, 2018 12:15 pm

exxos wrote:
Mon Dec 17, 2018 3:10 pm
For things like DTACK, I may use a single open collector buffer.. they normally good for 30V pull down voltages. So that would solve that problem without needing anything "fancy" doing.
I don't think that would work. You could use an open collector buffer for BR because it is an output only pin. But DTACK is bidirectional. If you would use an unidirectional buffer Blitter won't be able to detect when DTACK is asserted by other systems components. DTACK (and BGACKo as well) requires some bidirectional solution as mentioned at the previous post.
I am not sure when I will get chance to look into this project , hopefully in the next couple of weeks I will be caught up on other things that I can spend more time on it.
No problems. And no offense at all if you eventually decide to go with the other solution using switches instead. This is a very minor modification. Didn't take too much time.
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Re: BLITTER RE-CREATION THOUGHTS

Post by exxos » Tue Dec 18, 2018 1:01 pm

ijor wrote:
Tue Dec 18, 2018 12:15 pm
I don't think that would work. You could use an open collector buffer for BR because it is an output only pin. But DTACK is bidirectional.
Ah yes you are right there. I was only thinking blitter side.
ijor wrote:
Tue Dec 18, 2018 12:15 pm
No problems. And no offense at all if you eventually decide to go with the other solution using switches instead. This is a very minor modification. Didn't take too much time.
I need to have a good think about all this at some point..My thoughts are the bidirectional buffers, or single mosfets. I know the mosfet idea will work, but I would prefer to go with a IC.. its just finding one which I am happy with. Currently TF is suspecting some issues with the IC buffers he used, so I am waiting to see what the outcome of that is before anything else. If IC's are going to be a pain, then I will just go with mosfets.

Something else you mentioned before about the "Boot time" of the FPGA. Thinking out loud mostly, but I wonder if its possible for the FPGA to hold RESET until it has booted? This way the machine doesn't try to boot up and use the blitter before the FPGA code has loaded. I would assume TOS would go a bit mental if the blitter appeared after TOS has initialized.
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Re: BLITTER RE-CREATION THOUGHTS

Post by ijor » Tue Dec 18, 2018 2:14 pm

exxos wrote:
Tue Dec 18, 2018 1:01 pm
ijor wrote:
Tue Dec 18, 2018 12:15 pm
I don't think that would work. You could use an open collector buffer for BR because it is an output only pin. But DTACK is bidirectional.
Ah yes you are right there. I was only thinking blitter side.
There is another possible solution for these open drain signals without using any bidirectional chips. Use two TTL buffers (or two ports of one buffer) and two separated FPGA pins, one for the input and another for the output. You need two separated signals to avoid a loop. But since the output is open drain, you don't need output enable or direction control.
I need to have a good think about all this at some point..My thoughts are the bidirectional buffers, or single mosfets. I know the mosfet idea will work, but I would prefer to go with a IC.. its just finding one which I am happy with. Currently TF is suspecting some issues with the IC buffers he used, so I am waiting to see what the outcome of that is before anything else. If IC's are going to be a pain, then I will just go with mosfets.
I think each approach has its pros and benefits. Using directionless switches, either ICs or discrete mosfets is simpler, of course. The drawback is the reduced margin noise. These chips don't output 5V at either side because they aren't really voltage converters, they are actually voltage limiters. That's the advantage of a directional transceiver with two separate vcc rails.
Something else you mentioned before about the "Boot time" of the FPGA. Thinking out loud mostly, but I wonder if its possible for the FPGA to hold RESET until it has booted?
The FPGA does output a couple of signals that you could use to detect if it is already configured or not. But I know realize that instead of using an FPGA, you could use a CPLD such as the Altera/Intel Max 10. This family, more than a CPLD, is actually an FPGA with non volatile memory to store the configuration internally. They boot pretty fast, need to check the datasheet for the exact timing. It is also cheaper and simpler solution because you avoid the external flash memory.
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Re: BLITTER RE-CREATION THOUGHTS

Post by exxos » Tue Dec 18, 2018 2:20 pm

Yeah the MAX 10 series was what I was looking at to add the blitter into a while back. I tried a few out near the start of the thread. viewtopic.php?f=29&t=79#p5123 They do indeed have internal ROM , so makes thing a little easier.
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Re: BLITTER RE-CREATION THOUGHTS

Post by exxos » Thu Dec 20, 2018 7:14 pm

TF used the sn74cb3t3245 on his last boards. I was talking to him about some chips before, but turns out hes actually used one of the mosfet based things which I am having troubles with. So I ordered a chip from farnell just and a SOIC to DIP adapter to try the chip out on breadboard to see if it behaves.

Though I didn't realise TF used a mosfet one until a few days ago.. It seems to be working fine, but I don't think it's actually been 100% confirmed with the voltages yet..

The chip which isn't mosfet based is the 74LCX245-D, which of course needs direction control. It was that chip I am considering using with Ijors patched blitter code.

Hopefully my chip will arrive tomorrow (probably not) So will test it out. If I can't get it to behave then I will look into either separate mosfets (which I know works) or the 74LCX245 with the patched blitter code. Going for a IC seems a lot less work , so we shall see how things test out...
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Re: BLITTER RE-CREATION THOUGHTS

Post by ijor » Fri Dec 21, 2018 2:17 am

exxos wrote:
Thu Dec 20, 2018 7:14 pm
The chip which isn't mosfet based is the 74LCX245-D, which of course needs direction control. It was that chip I am considering using with Ijors patched blitter code.
If you decide to use the patched core remember that a solution for the open drain signals is still pending. I didn't do anything with them because I didn't know how exactly you want to deal with them. There are several possible solution for the open drain signals. Whatever solution is decided, it is very simple to implement at the FPGA side. So no big deal at all.

Note that the 74LCX245 is not exactly a level shifter. It is a low voltage 5V tolerant transceiver. It always outputs low voltage at both sides. Contrast with true dual voltage parts like the 74LVC8T245 or the one used by Smonson on the HDMI board. If this is really important or not, I don't know.
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