BLITTER RE-CREATION THOUGHTS

Progress on our FPGA cores.
slingshot
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Re: BLITTER RE-CREATION THOUGHTS

Post by slingshot » Tue Nov 12, 2019 9:56 pm

Icky wrote:
Tue Nov 12, 2019 9:14 pm
Just trying to figure out how to sort out the CLK_EN_p and CLK_EN_n what with that and the distraction of almost getting my printer to do a first ever print this evening :)
Here's an example in ijor's FX68K how to create the two clock enables (it's for 32MHz, so divides by 4, but easy to convert to 16MHz/2):
https://github.com/ijor/fx68k/blob/mast ... k.sv#L2648

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Icky
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Re: BLITTER RE-CREATION THOUGHTS

Post by Icky » Tue Nov 12, 2019 10:11 pm

slingshot wrote:
Tue Nov 12, 2019 9:56 pm
Icky wrote:
Tue Nov 12, 2019 9:14 pm
Just trying to figure out how to sort out the CLK_EN_p and CLK_EN_n what with that and the distraction of almost getting my printer to do a first ever print this evening :)
Here's an example in ijor's FX68K how to create the two clock enables (it's for 32MHz, so divides by 4, but easy to convert to 16MHz/2):
https://github.com/ijor/fx68k/blob/mast ... k.sv#L2648
Thanks. I had just been looking at that file trying to find an example. Let's see if I can get this working on the board, if I don't get interrupted by non-Atari stuff.

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Re: BLITTER RE-CREATION THOUGHTS

Post by Icky » Wed Nov 13, 2019 7:52 am

Got slingshots changes to compile last night but it was 1 am in the morning too late to start testing. Will look at plugging the Sparklaphobia (FPGA Blitter) board in to test tonight after normal non-Atari day life is out of the way.

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Re: BLITTER RE-CREATION THOUGHTS

Post by Icky » Wed Nov 13, 2019 8:09 am

slingshot wrote:
Tue Nov 12, 2019 9:52 pm
That's why I'm interested in the re-creation from the schematics.
Exxos and I are still going to continue with the schematics re-creation as that’s going to be a good base to start with.

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Cyprian
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Re: BLITTER RE-CREATION THOUGHTS

Post by Cyprian » Wed Nov 13, 2019 9:40 am

slingshot wrote:
Tue Nov 12, 2019 9:52 pm
Cyprian wrote:
Tue Nov 12, 2019 8:52 pm
"Release the bus for 64 CLK cycles." - it uses wrong cycle split scheme
I've also changed that back to 64/64.

I don't know how the original performs, but my main interest is demo compatibility, which require cycle perfect operation, and it's hard to achieve without having this as a design goal from the beginning. That's why I'm interested in the re-creation from the schematics.
the split on the real hardware looks like:
- 65 bus cycles for the BLiTTER - 63 for fetching data plus 2 for bus mastering;
- 64 bus cycles for the CPU. One important remark. The BLiTTER counts 64 cycles USED by the CPU. It means long instructions (like div) can significantly delay the BLiTTER.

That split is implemented in the latest Hatari and Steem emulators since this year.

If I'm not wrong, in the Suska's code I see that wrong 64/64 split scheme, and also I can't see code responsible for counting cycles used by the CPU.
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Re: BLITTER RE-CREATION THOUGHTS

Post by slingshot » Wed Nov 13, 2019 10:40 am

Cyprian wrote:
Wed Nov 13, 2019 9:40 am

If I'm not wrong, in the Suska's code I see that wrong 64/64 split scheme, and also I can't see code responsible for counting cycles used by the CPU.
On the schematics, it can be seen that the HOG counter counts the XASI signal (incoming AS when the CPU is the bus master, outgoing when the Blitter is), that's how many times the CPU/Blitter accesses the memory. Yeah, it's not implemented this way in Suska. But that's not the only difference from the original behavior.
And that's another example why it's risky to implement this 1:1 in FPGA: here the internal AS signal is a _clock_. Not a good idea for an FPGA.

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Re: BLITTER RE-CREATION THOUGHTS

Post by Cyprian » Wed Nov 13, 2019 11:41 am

slingshot wrote:
Wed Nov 13, 2019 10:40 am
On the schematics, it can be seen that the HOG counter counts the XASI signal (incoming AS when the CPU is the bus master, outgoing when the Blitter is), that's how many times the CPU/Blitter accesses the memory. Yeah, it's not implemented this way in Suska.
I spent so many hours to find a bug in my blitter code, which finally appeared that CPU access counting.
Would be better to learn read schematics before :)

slingshot wrote:
Wed Nov 13, 2019 10:40 am
But that's not the only difference from the original behavior.
And that's another example why it's risky to implement this 1:1 in FPGA: here the internal AS signal is a _clock_. Not a good idea for an FPGA.
interesting.
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Re: BLITTER RE-CREATION THOUGHTS

Post by dhedberg » Wed Nov 13, 2019 11:59 am

Cyprian wrote:
Wed Nov 13, 2019 11:41 am
slingshot wrote:
Wed Nov 13, 2019 10:40 am
On the schematics, it can be seen that the HOG counter counts the XASI signal (incoming AS when the CPU is the bus master, outgoing when the Blitter is), that's how many times the CPU/Blitter accesses the memory. Yeah, it's not implemented this way in Suska.
I spent so many hours to find a bug in my blitter code, which finally appeared that CPU access counting.
Would be better to learn read schematics before :)
What did you try to do and what was the consequence of this? How did this "bug" present itself? I'm interested as I'm messing with the Blitter quiet a lot lately.

Thanks,
Daniel
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Re: BLITTER RE-CREATION THOUGHTS

Post by slingshot » Wed Nov 13, 2019 12:27 pm

Cyprian wrote:
Wed Nov 13, 2019 11:41 am

I spent so many hours to find a bug in my blitter code, which finally appeared that CPU access counting.
I will change the code to count AS edges instead of pure clock ticks. Maybe it'll fix everything magically :) (Well, don't think so, but probably will better).

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Re: BLITTER RE-CREATION THOUGHTS

Post by Cyprian » Wed Nov 13, 2019 12:32 pm

dhedberg wrote:
Wed Nov 13, 2019 11:59 am
What did you try to do and what was the consequence of this? How did this "bug" present itself? I'm interested as I'm messing with the Blitter quiet a lot lately.

Thanks,
Daniel
Below you can find a graphics representation of that behaviour. That screenshot is taken from real hardware.
White/grey/red stripes are the CPU activity, a black one is the BLiTTER.
BLiT_H6a4c.png
BLiT_H6a4c.png (113.02 KiB) Viewed 1747 times
1) In case of famous "64/64" bus cycle split, there should be black rectangle through whole screen.
On the real hardware the BLiTTER part is skewed (65/64)- we can see that on my screenshot - just below numbers, a first few scanlines have skewed black lines.

2) Some instructions can delay the BLiTTER.
In my case black lines (the BLiTTER part) are separated by white ones ("DIVS" instruction).


more you can find there:
http://www.atari-forum.com/viewtopic.ph ... 25#p313292
http://www.atari-forum.com/viewtopic.ph ... 25#p228964

And another one with parallel running the BLiTTER and the CPU
http://www.atari-forum.com/viewtopic.php?p=96197#p96197
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