Here's an example in ijor's FX68K how to create the two clock enables (it's for 32MHz, so divides by 4, but easy to convert to 16MHz/2):
https://github.com/ijor/fx68k/blob/mast ... k.sv#L2648
Here's an example in ijor's FX68K how to create the two clock enables (it's for 32MHz, so divides by 4, but easy to convert to 16MHz/2):
Thanks. I had just been looking at that file trying to find an example. Let's see if I can get this working on the board, if I don't get interrupted by non-Atari stuff.slingshot wrote: ↑Tue Nov 12, 2019 9:56 pmHere's an example in ijor's FX68K how to create the two clock enables (it's for 32MHz, so divides by 4, but easy to convert to 16MHz/2):
https://github.com/ijor/fx68k/blob/mast ... k.sv#L2648
the split on the real hardware looks like:slingshot wrote: ↑Tue Nov 12, 2019 9:52 pmI've also changed that back to 64/64.
I don't know how the original performs, but my main interest is demo compatibility, which require cycle perfect operation, and it's hard to achieve without having this as a design goal from the beginning. That's why I'm interested in the re-creation from the schematics.
On the schematics, it can be seen that the HOG counter counts the XASI signal (incoming AS when the CPU is the bus master, outgoing when the Blitter is), that's how many times the CPU/Blitter accesses the memory. Yeah, it's not implemented this way in Suska. But that's not the only difference from the original behavior.
I spent so many hours to find a bug in my blitter code, which finally appeared that CPU access counting.slingshot wrote: ↑Wed Nov 13, 2019 10:40 amOn the schematics, it can be seen that the HOG counter counts the XASI signal (incoming AS when the CPU is the bus master, outgoing when the Blitter is), that's how many times the CPU/Blitter accesses the memory. Yeah, it's not implemented this way in Suska.
interesting.
What did you try to do and what was the consequence of this? How did this "bug" present itself? I'm interested as I'm messing with the Blitter quiet a lot lately.Cyprian wrote: ↑Wed Nov 13, 2019 11:41 amI spent so many hours to find a bug in my blitter code, which finally appeared that CPU access counting.slingshot wrote: ↑Wed Nov 13, 2019 10:40 amOn the schematics, it can be seen that the HOG counter counts the XASI signal (incoming AS when the CPU is the bus master, outgoing when the Blitter is), that's how many times the CPU/Blitter accesses the memory. Yeah, it's not implemented this way in Suska.
Would be better to learn read schematics before
I will change the code to count AS edges instead of pure clock ticks. Maybe it'll fix everything magically (Well, don't think so, but probably will better).
Below you can find a graphics representation of that behaviour. That screenshot is taken from real hardware.