BLITTER RE-CREATION THOUGHTS

[slingshot]

The ST 32MHz we tried with Suska blitter and it malfunction really badly. https://www.exxosforum.co.uk/forum/viewt ... 220#p27218 But the ST's 32MHz clock isn't very strong, it cannot really drive anything other than shifter.. but thats a lot of other problems which I won't go into here.

Yeah time is a problem for everyone. I think we will have the blitter core copied into Quartus by the end of the year.. as to if we copy it correctly is another matter

As I see, the Suska blitter is designed for the original 8MHz clock. I might test it with the MiST core and see how it performs there.

[slingshot]

Yeah time is a problem for everyone.

It just not a "not enough time" problem. It's simply a lot of work to do (and verify).

[exxos]

As I see, the Suska blitter is designed for the original 8MHz clock.

But it doesn't work on 8MHz at correct speed.. thats the problem.

[slingshot]

Just tried the Suska's blitter with the MiST core, and its state machine just got stuck. I think I see where's the problem (the clocking - some signals are active when CLK=0, then it checks for it at a rising_edge block, I wonder how it's supposed to work). I might try to fix it, and will see how it performs.

[Icky]

Just tried the Suska's blitter with the MiST core, and its state machine just got stuck. I think I see where's the problem (the clocking - some signals are active when CLK=0, then it checks for it at a rising_edge block, I wonder how it's supposed to work). I might try to fix it, and will see how it performs.

If you could take a look that would be great.

[slingshot]

I've succesfully integrated the Suska's blitter in the MiST core. Added a small patch, which fixed the clocking:
https://github.com/gyurco/MiSTery/commi ... 6f252776f7
Basically converted to a two-phase clock-enable structure, that means you need at least 16MHz clock for a 8MHz effective operation (the same used in Ijor's FX68K).
However this blitter is not cycle-exact, STe demos are usually garbled. GEM and the STe test cartridge passes. Kwikutils benchmark show some operations slightly faster, some slower than the original. Don't think it would be good for a perfect replacement of the original chip.

[Cyprian]

"Release the bus for 64 CLK cycles." - it uses wrong cycle split scheme

[exxos]

I've succesfully integrated the Suska's blitter in the MiST core. Added a small patch, which fixed the clocking:
https://github.com/gyurco/MiSTery/commi ... 6f252776f7
Basically converted to a two-phase clock-enable structure, that means you need at least 16MHz clock for a 8MHz effective operation (the same used in Ijor's FX68K).
However this blitter is not cycle-exact, STe demos are usually garbled. GEM and the STe test cartridge passes. Kwikutils benchmark show some operations slightly faster, some slower than the original. Don't think it would be good for a perfect replacement of the original chip.

Icky has the test board hooked up, so hopefully he can plug your code into our board to test.

But what does it benchmark at overall ? compared to the original suska code ?

[Icky]

I've succesfully integrated the Suska's blitter in the MiST core. Added a small patch, which fixed the clocking:
https://github.com/gyurco/MiSTery/commi ... 6f252776f7
Basically converted to a two-phase clock-enable structure, that means you need at least 16MHz clock for a 8MHz effective operation (the same used in Ijor's FX68K).
However this blitter is not cycle-exact, STe demos are usually garbled. GEM and the STe test cartridge passes. Kwikutils benchmark show some operations slightly faster, some slower than the original. Don't think it would be good for a perfect replacement of the original chip.

Icky has the test board hooked up, so hopefully he can plug your code into our board to test.

But what does it benchmark at overall ? compared to the original suska code ?

Thanks slingshot.

Just trying to figure out how to sort out the CLK_EN_p and CLK_EN_n what with that and the distraction of almost getting my printer to do a first ever print this evening

[slingshot]

"Release the bus for 64 CLK cycles." - it uses wrong cycle split scheme

I've also changed that back to 64/64.

I don't know how the original performs, but my main interest is demo compatibility, which require cycle perfect operation, and it's hard to achieve without having this as a design goal from the beginning. That's why I'm interested in the re-creation from the schematics.