BLITTER RE-CREATION THOUGHTS

Progress on our FPGA cores.
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Cyprian
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Re: BLITTER RE-CREATION THOUGHTS

Post by Cyprian » Mon Apr 13, 2020 11:30 pm

Icky wrote:
Sat Apr 11, 2020 1:03 pm
Cyprian wrote:
Sat Apr 11, 2020 8:50 am
just to let you know
@ijor has released his BLiTTER fpga code:

https://github.com/ijor/stBlitter
Thanks @Cyprian. As one of my many projects I have been looking at fitting Igor's code into the FPGA board to see how it works. I currently have it plumbed in but the ST is not booting currently :).

Unfortunately prioritywise its not top of my list this holiday break as I am re-wiring the Giant Panda wiring loom and then swinging back to the Flashy Clock V6 testing.

EDIT: and I keep getting distracted viewtopic.php?f=29&t=2636&start=30#p36237
cool,
still waiting impatiently for your blitter/fpga board :)
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Icky
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Re: BLITTER RE-CREATION THOUGHTS

Post by Icky » Sun Oct 11, 2020 9:42 pm

I finally got round to looking at this project again this weekend and have made progress. The Sparkalaphobia board is now almost matching a stock BLITTER.

The screenshot of GEMBench shows the test motherboard recorded with an original BLITTER so 100% is the stock. The FPGA BLITTER is just under at 98% and we are not getting any corruption including doing various tests.

Whats more I managed to test the Suska core as well as Ijor's core and there were absolutely no differences in the scores or behaviour.

IMG_5776.jpeg
IMG_5776.jpeg (153.08 KiB) Viewed 236 times

I have run @Cyprian's test programs and the patterns are a little different to the original BLITTER so may be there is something that can be tweaked to get this to 100%.

EDIT: 1st image corrected.
Program 1.png
Program 1.png (1.5 MiB) Viewed 164 times
Program 2.png
Program 2.png (1.32 MiB) Viewed 236 times

sporniket
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Re: BLITTER RE-CREATION THOUGHTS

Post by sporniket » Mon Oct 12, 2020 3:52 am

Great work !

To me, the "program 1" snapshot let me believe that the missing 2% are lost in getting the first bus grant ? And on the other hand in the "program 2" it got to start a very very little bit quicker.

==> Does the wakestate have an influence on the result ?

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Re: BLITTER RE-CREATION THOUGHTS

Post by Icky » Thu Oct 15, 2020 7:59 am

Well after getting to 98% and hacking away at the v2 of the board to get it to work I respun the board to a v3 which is a lot smaller and the footprint is changed to match the H4/H5 PLCC socket layout. From the image you can see its only a little bit wider than a PLCC socket. If this version works I will spin a funky socket version.

Top side:
Screenshot 2020-10-15 at 00.21.36.png
Screenshot 2020-10-15 at 00.21.36.png (856.53 KiB) Viewed 163 times

Bottom:
Screenshot 2020-10-15 at 00.23.45.png
Screenshot 2020-10-15 at 00.23.45.png (751.88 KiB) Viewed 163 times

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GadgetUK164
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Re: BLITTER RE-CREATION THOUGHTS

Post by GadgetUK164 » Thu Oct 15, 2020 10:18 am

This is fantastic! Great job!!!!
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Re: BLITTER RE-CREATION THOUGHTS

Post by dhedberg » Thu Oct 15, 2020 10:24 am

Wow, looks awesome. That must have involved some layout voodoo? :lol:
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Re: BLITTER RE-CREATION THOUGHTS

Post by DoG » Thu Oct 15, 2020 1:11 pm

Looking good... as usual. Really nice progress on this.

I hope everyone can afford a FPGA-blitter later on.

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Re: BLITTER RE-CREATION THOUGHTS

Post by Icky » Thu Oct 15, 2020 7:08 pm

sporniket wrote:
Mon Oct 12, 2020 3:52 am
Great work !

To me, the "program 1" snapshot let me believe that the missing 2% are lost in getting the first bus grant ? And on the other hand in the "program 2" it got to start a very very little bit quicker.

==> Does the wakestate have an influence on the result ?
I did have the program #1 images the wrong way round. I have corrected the image in the post.

sporniket
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Re: BLITTER RE-CREATION THOUGHTS

Post by sporniket » Thu Oct 15, 2020 8:15 pm

I see.

Anyway it's good enough for now, the last 2% would take 98% of effort to reach.

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Re: BLITTER RE-CREATION THOUGHTS

Post by Cyprian » Fri Oct 16, 2020 8:17 pm

Icky wrote:
Sun Oct 11, 2020 9:42 pm
I finally got round to looking at this project again this weekend and have made progress. The Sparkalaphobia board is now almost matching a stock BLITTER.
...


I have run @Cyprian's test programs and the patterns are a little different to the original BLITTER so may be there is something that can be tweaked to get this to 100%.
great news looks almost perfect.
I wonder about two things:
- "1st image" - the right part - marked "Sprahlaphobia". CPU bars (white/grey/red) above the BLiTTER activity are skewed but should be straight like those below the BLiTTER activity area. Looks like something delays the CPU by 4 cycles (one bus access) each line.

- "2nd image" are you sure they are marked correctly? For me the right part, marked "Sprahlaphobia" is actually the real STE, and the left part is "Sprahlaphobia" - there the CPU starts the BLiTTER 4 cycles (1 bus access) later.
sporniket wrote:
Mon Oct 12, 2020 3:52 am
==> Does the wakestate have an influence on the result ?
they shouldn't but who nows
Portfolio / Lynx II / Jaguar / TT030 / Mega STe / 800 XL / 1040 STe / Falcon030 / 65 XE / 520 STm / SM124 / SC1435
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