CURRENT PROTOTYPE STATUS (SEC 64MHz 68000)

Information and news about the 68SEC000 64MHz booster.
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Re: CURRENT PROTOTYPE STATUS (SEC 64MHz 68000)

Post by exxos » Thu Jan 21, 2021 4:18 pm

Had to resolder the CPU as was a iffy joint somewhere.. but now running at 50MHz :)

as said previously, this is not much faster than 32MHz on the STE.. basically because the ROM IC itself is bottlenecked to 32MHz speeds. but there are things in the pipeline to overcome that limitation.. But more on that some other time..

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Next to plug this in and do the firmware & software to enabled it :)

These are 45ns SRAMs, so I doubt I will get past maybe 40MHz speeds with it.. but its a start...

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Re: CURRENT PROTOTYPE STATUS (SEC 64MHz 68000)

Post by exxos » Thu Jan 21, 2021 6:33 pm

Iffy connections aside...

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Re: CURRENT PROTOTYPE STATUS (SEC 64MHz 68000)

Post by exxos » Thu Jan 21, 2021 7:20 pm

Now I realise I have done something dumb , probably out of force of habit with only dealing with ROMs for the past 25 years.. :roll:

I will leave this little puzzle here for everyone :)

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:headbang: :headbang:
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Re: CURRENT PROTOTYPE STATUS (SEC 64MHz 68000)

Post by stephen_usher » Thu Jan 21, 2021 9:39 pm

The READ/WRITE is the wrong way around?
Intro retro computers since before they were retro...
ZX81->Spectrum->Memotech MTX->Sinclair QL->520STM->BBC Micro->TT030->PCs & Sun Workstations.
Added code to the MiNT kernel (still there the last time I checked) + put together MiNTOS.
Collection now with added Macs, Amigas, Suns and Acorns.

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Re: CURRENT PROTOTYPE STATUS (SEC 64MHz 68000)

Post by olivier.jan » Thu Jan 21, 2021 9:53 pm

With the RAM chip always enabled, how you prevent it being written when the CPU writes to other devices ?

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Re: CURRENT PROTOTYPE STATUS (SEC 64MHz 68000)

Post by exxos » Thu Jan 21, 2021 10:10 pm

olivier.jan wrote:
Thu Jan 21, 2021 9:53 pm
With the RAM chip always enabled, how you prevent it being written when the CPU writes to other devices ?
:bravo:
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Re: CURRENT PROTOTYPE STATUS (SEC 64MHz 68000)

Post by exxos » Thu Jan 21, 2021 11:17 pm

Started a new SRAM board.. this one will be 3.3V only to speed things up with the PCB. Using 2 chips means I am 2 RAM OE lines free, so I can reuse them for the 2 missing CE lines...

Mouser only sell the chips it seems, almost £20 a pop, but still a lot cheaper than the 5V board. Also had to do a new lib for it :roll:

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Re: CURRENT PROTOTYPE STATUS (SEC 64MHz 68000)

Post by exxos » Fri Jan 22, 2021 8:11 pm

Other than running DRC 500 times.. should be done..

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Re: CURRENT PROTOTYPE STATUS (SEC 64MHz 68000)

Post by exxos » Sat Jan 23, 2021 3:52 pm

I've had a thought that I'll need some pull ups on the 4 control lines to 3.3v. As the SEC booster has to run on the 5v bus, I can't feed 5v into the SRAM lines.. So pull ups to 3.3v and open collector drive on the booster should fix the problem.

I hope to order these boards on Monday along with the SRAM. Once its all working , I will try and build a few for stock, though I'm not planning on making many of either as time and cost will be pretty high..plus the board will only work on the H5.. I do hope to move to SDRAM type board in the future. Though with things going at a snail pace all the time, I don't think that board will get done this year.
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Re: CURRENT PROTOTYPE STATUS (SEC 64MHz 68000)

Post by exxos » Mon Jan 25, 2021 3:11 pm

I've patched up the current SRAM board.. The chips are to slow for 50MHz+ speeds, so had to add some waitstates..

Considering the TF536 pushes around 800% without caches and is 32bit, It makes sense that a 68000 Can operate around 400% as its 16bit. Though I think once I get the new SRAM board built, I can easily run 64MHz. So 400%-500% speeds should really be reachable.

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I have had it also at 359% but this is only a quick patch up to see things are working as expected.
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