I do not get why that delay is even there in the first place.. In terms of writing to RAM, it would mean the DRAM would not get the data from the CPU until 100ns later ( plus the delay of the LS244 buffers).
So I swapped out the 120ns DRAMs for 100ns ones to make things easier..
This benchmark is basically the original (baseline test)
This benchmark is with a separate delay on ST_RAM WRITE DTACK. basically 4x 50MHz clocks ~ 80ns.
Now if we assume 20ns delay on the LS244 ( will likely be a bit quicker but I am building in some margin of error into this figure anyway) we end up with 100ns! if I take away 20 ns, the machine just turned into a crash generator, because basically it is running the RAM at 80ns.
Basically mean, assuming a delay of 100ns on the MMU, plus 20 on the buffers (120ns) and a 8MHz cycle time of 250ns, this means the DRAM would have to be (250ns - 120ns) 130ns or faster. Now I have seen 150ns chips so likely it's doable. Basically the figures do generally work out as expected. I would assume RAM slower than 150 ns was never fitted in the ST range ?
So what the heck is this all about ? basically I am trying to speed up RAM access without overclocking the MMU. In terms of Write cycles, the CPU databus simply goes through the LS244 buffers to the DRAM, MMU really does not have anything to do with speed at that point.
The above benchmarks may not look very interesting, but it proves the point that ram access does appear to be speeding up.. The RAM speed test would likely show any speed improvement until we hit double speed of 200%. This is basically because we cannot fit 2 RAM accesses in the same time frame unless the RAM is running at 200% speeds. So what I assume is happening is that the RAM cycle completes slightly early, and it is able to start a ROM cycle sooner, which is slightly increasing the scores in the benchmarks.
The problem is this odd 100ns delay. Because the MMU is controlling who has access to RAM, we cannot simply bypass it, as it may actually need to be there at some point because of shifter accesses to RAM.So it looks like I may have hit a brick wall with this direction
EDIT:
Part of the delay on write might be down to the delayed RW on the 68000 itself.. so need to look into that timing as well ...
EDIT2:
I also tried speeding up the RAM READ, ended up as 7 clocks delay ( 120ns). Most scores went up about 2%. Int-div was the largest one which jumped to 512% from 506%.