Page 4 of 54

Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS

Posted: Thu Dec 28, 2017 3:22 pm
by exxos
The PLL PCBs arrived just :) I need to order the chip from mouser yet though..

Just a re-cap that using the ST FM 32 MHz generator couldn't be done because of lack of buffering. On one motherboard I took out the generator and started with a 32 MHz oscillator and use that instead, basically this is what the MEGA ST does. But this started causing video interference which I need to re-cap etc...

But in talking to terrible fire about PLL chips a couple weeks ago, it should be possible to use this little board to multiply the 8MHz to 32 MHz without interfering with the motherboard circuit at all.

Currently in light of the problems with the V2 .2 booster remake this version 2.5 board will now take over from that project.

So today I created some basic firmware which will run at 16 MHz like the V2 .2 booster..

IMG_2143.JPG
IMG_2143.JPG (176.78 KiB) Viewed 2302 times

The little add-on board the CPU clock buffer as mentioned couple of posts previously.

And with some testing just..

v25.jpg
v25.jpg (106.04 KiB) Viewed 2302 times
I will leave it running for the rest of the day to make sure it is stable before doing any more work to it. But basically this is now working as it should :)

The only problem with this board is because the PLD is much larger, the PCB is much larger and is actually in the way of the MMU. This probably isn't a problem for a lot of machines, if someone is using my 4MB MMU RAM board as shown in other images elsewhere, it would actually be in the way of that upgrade.

Ultimately the CPU will be solder direct to the board to avoid all those stupid socket issues, and there are smaller SMT PLD's will take up a lot less space.. I may try and squashed the PLD above the DIP CPU area to save some space.. These are problems for another day anyway.

So I will try and order my mouser parts tomorrow, then I can see if I can get this design running stable at 32 MHz. I really don't want to release a new booster without actually offering something new. So I really want to get 32 MHz working on this design before it is produced. But worst case, it'll take over from the V2 .2 booster.

Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS

Posted: Tue Jan 02, 2018 2:34 pm
by exxos
With all the troubles I have had with the PLCC sockets, I thought about just soldering the CPU direct to the PCB.. But really the CPU was smaller it could fit above the dip CPU.. Same with the PLD..I have been wanting to move to the SEC CPU for a long time now, so I think now is the ideal time to investigate that processor.

Rodolphe actually already created some code year ago for his booster using the same PLD which I am currently wanting to use. This code is almost the same as wiring up a 020 CPU. It is tried and tested code, so should be simple to include it in this project to get it up and running faster. He also spend some time helping with the library for these parts as well :)


So yet again I am doing another booster PCB :roll:

sec.JPG
sec.JPG (112.31 KiB) Viewed 2281 times

There should be just enough room to squash the PLD on the bottom layer, and the CPU on the top layer.. This PCB is what I am currently working on.

I am not sure if I will include ROM on this particular design is really I just want to prove the CPU works well. Also the Amiga people claim this processor is capable of somewhere between 50Mhz - 80Mhz. So keeping the logic simple as possible will help investigate if this processor can really run faster.

The CPU could run at I hope 64Mhz. It would be unlikely that the ROM could run faster than 32MHz, not with using 55ns chips anyway. Similar with fast ram, if faster chips could be used, then we could have access to 64Mhz fast ram.. Overall, there will likely have to be wait states introduced, but I will find out the maximum speed possible anyway.

Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS

Posted: Tue Jan 02, 2018 8:18 pm
by Maeke
exxos wrote:
Tue Jan 02, 2018 2:34 pm
With all the troubles I have had with the PLCC sockets, I thought about just soldering the CPU direct to the PCB.. But really the CPU was smaller it could fit above the dip CPU.. Same with the PLD..I have been wanting to move to the SEC CPU for a long time now, so I think now is the ideal time to investigate that processor.
Which means this booster could work on any st(m)/stf(m).

Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS

Posted: Tue Jan 02, 2018 9:45 pm
by exxos
Maeke wrote:
Tue Jan 02, 2018 8:18 pm
Which means this booster could work on any st(m)/stf(m).
Yes.

I might see if I can add flash onto the next prototype, assuming this first one works that is.. the PLCC ROM is a bit to big to fit also.. Would be pretty compact with flash I think.

Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS

Posted: Thu Jan 04, 2018 4:50 pm
by exxos
Still working on this with each few moments I have spare during the day... With constant interruptions it's difficult to make any faster progress with it.

I have removed the SIL arrays, as the testing it does not really matter as one of my machines as all 2k2 anyway. It save some time in routing.. I have also decided not to route ROM on this initial design to save a lot of work routing.

All I really need to know initially ,is that the PLD is controlling the new CPU correctly. Plus I mostly just want to see what speed this new CPU is capable of.. As if it cannot get higher than 32 MHz... It is a little questionable if it is worth using it in future designs..

Currently the CPU is on the top layer, and the PLD is on the bottom layer. So I have managed to route this on just two layers this means the prototypes of them cost too much to build.

Capture.JPG
Capture.JPG (105.51 KiB) Viewed 2237 times

Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS

Posted: Thu Jan 04, 2018 9:04 pm
by keli
How are you handling the two vs three pin bus arbitration protocol translation? Is it handled by the pld or do you simply ignore the /BGACK pin?

Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS

Posted: Thu Jan 04, 2018 9:11 pm
by rpineau
in the CPLD :
CPU_BR = ST_BR & ST_BGACK;
as in 2 wire protocol, /BR need to stay asserted for the whole time where /BGACK would be on a 3 wires system.

Can also be written :
!BR_CPU = !ST_BR # !ST_BGACK;

Rodolphe

Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS

Posted: Thu Jan 04, 2018 10:19 pm
by exxos
keli wrote:
Thu Jan 04, 2018 9:04 pm
How are you handling the two vs three pin bus arbitration protocol translation? Is it handled by the pld or do you simply ignore the /BGACK pin?
Done as Rodolphe says above. Rodolphe is the bus master here ;) We tested it out some time ago in fact :)


bg.jpg
bg.jpg (102.87 KiB) Viewed 2219 times

Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS

Posted: Fri Jan 05, 2018 9:18 pm
by exxos
A a tiny bit more progress today..

I realised I had forgot to add the PLL on board so added that also (thanks again to Rodolphe for doing the edit so quickly)

The PLL will be fed with 8 MHz, and it can step up to 16 MHz, 32 MHz, 64 MHz etc. 32 MHz generator as mentioned before, is very bad on the STFM which needs a lot of work fixing. Even so, there is no 64 MHz clock anyway, so using a PLL is the only way to easily do this.

11.JPG
11.JPG (144.41 KiB) Viewed 2198 times

As mentioned before, the HC CPU maxed out at 38 MHz on my STE... I think the speed gain would have been a little more if I could have got up to 40 MHz... But even so figures still creep up just of this small megahertz difference... So I am really interested to see what the 64 MHz will bring.. If it is possible, but of course I think after 32 MHz we are really getting in to the territory of diminishing returns...


Image

Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS

Posted: Sat Jan 06, 2018 12:08 am
by troed
exxos wrote:
Fri Jan 05, 2018 9:18 pm
Even so, there is no 64 MHz clock anyway, so using a PLL is the only way to easily do this.
And it will also be a correct multiple of 8.01/8.02/8.05 instead of the 64.000MHz oscillator that I bought and used for the double-speed Shifter mod. The PLL-method definitely sounds like the way to go.

/Troed