CURRENT PROTOTYPE STATUS (SEC 64MHz 68000)

Information and news about the 68SEC000 64MHz booster.
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troed
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS

Post by troed » Fri Jan 19, 2018 11:26 am

exxos wrote:
Thu Jan 18, 2018 11:46 pm
I know the STE booster logic can work with seperate clock.. I will investigate if the STFM can operate the same.. It may be better to spend time on using a 32mhz osc but still 8/32 switching, but not in sync with system clock. It works fine on STE.. So maybe with some tweaking it can work well on the STFM as well. This way machine can run as stock 8mhz, but CPU gets speed boost on async clock.
Caveat: If CPU clock isn't 8.01/8.02/8.05 "stock" mode won't be fully compatible.

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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS

Post by exxos » Fri Jan 19, 2018 11:33 am

troed wrote:
Fri Jan 19, 2018 11:26 am
Caveat: If CPU clock isn't 8.01/8.02/8.05 "stock" mode won't be fully compatible.
Yeah there is that in the mix as well :(
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS

Post by exxos » Fri Jan 19, 2018 11:43 am

I've hooked up the V2.2 booster with a RSO which is actually running at 22MHz.. Something is not happy as I just get a row of bombs :roll:

CPU clock switching waveform looks to be operating just fine.. The only time the faster speed issues is when the CPU is not accessing the bus and doing internal instructions.. So it is not like it needs to sync with anything.. Then there is ROM access which runs at a faster speed, the circuit I think is more than capable of 22 MHz.

The only issue is the CPU actually runs at and 22 MHz as it starts the 8MHz bus cycle.. So is possible the CPU is looking for DTACK earlier than it should be. Actually had this issue on the V2.5 booster and it was easily fixed..

The main problem is back to sockets again, I need to redesign the booster to solder the CPU directly to the board.. But then would make more sense to go with the SEC CPU if going to the trouble of redesigning the board.. The problem is this all creates a phenomenal amount of work/projects/problems just to do a couple of simple tests :roll:

I will see if I can do some better tests with the current V2.5 prototype today... But I think the direction should be to concentrate on the SEC adaption next which means likely this series of booster would just have to be abandoned, and maybe even the STFM series totally. I can get stuff up and running on the STE in basically a day, whereas on the STFM it just takes endless months workinging through all the bugs and issues to get something stable.. Really just wondering if it is worth all the trouble :roll:
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS

Post by exxos » Fri Jan 19, 2018 1:27 pm

Current setup...

IMG_2171.JPG
IMG_2171.JPG (149.09 KiB) Viewed 1623 times

16MHz with blitter OFF.

v2616.jpg
v2616.jpg (108.48 KiB) Viewed 1617 times


16MHz with blitter ON.

v2616b.jpg
v2616b.jpg (108.26 KiB) Viewed 1617 times

I don't think I ever posted images of the clock switching before...

YELLOW : CPU CLOCK
BLUE : /AS
as16.png
as16.png (4.37 KiB) Viewed 1613 times

CLOSER LOOK
as162.png
as162.png (4.33 KiB) Viewed 1613 times

When /AS goes high, the CPU gets switched into 16MHz.
When /AS goes low, the CPU gets switched into stock 8MHz.


The exception to this is when doing ROM access is also CPU switched into 16MHz as shown below..
as163.png
as163.png (4.71 KiB) Viewed 1613 times


To be continued...
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS

Post by exxos » Fri Jan 19, 2018 5:07 pm

So I've been trying for the past few hours to use a 22MHz osc for not having much luck :( the clock switching looks fine, and I have tried delaying and syncing /AS & /DTACK on rising and falling edge is and adding a 8MHz delay.. I'll try adding in some more delays but this does not seem right direction to go in..

But really nothing should really care the CPU is running on a out of sync clock when address strobe is high.. So really do not understand what is going on here :roll:
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS

Post by exxos » Fri Jan 19, 2018 8:24 pm

This is running at 22 MHz.. And extremely unstable.. The image below is the absolute best I have seen it.. Mostly I just gave bombs on power up, or X's on ram test and end up with 128K instead of 512K.

I have tried absolutely everything I can think of over the past few hours to trying figure this out.. Just madness as all this works very well on the STE.

I did write some code a few months back which works running CPU at constant speed.. Ultimately I may put this code over to my SEC design and maybe run that way it is going to work better.. It is difficult to know at this point.

With the current design I can only think that there is some sort of bus conflict. I can run /AS through a flip-flop to sync it back to 8 MHz, but the problem is when the CPU is actually running at 8 MHz /AS well end up being a cycle too late. I do not think there is a easy way to implement clock syncing when the clock itself is running at two different speeds :roll:

The main problem with the CPU is it will start the next bus cycle when it has read /DTACK, when dealing with two separate speeds this becomes a problem as the CPU will start the next bus cycle early and there is no way to stop the cycle from starting unless the CPU has full bus isolation :roll:

c1.jpg
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS

Post by rpineau » Fri Jan 19, 2018 9:44 pm

Are you still doing the clock sync we were doing on the "old" booster as these are unrelated clocks ?
RoRo
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS

Post by exxos » Fri Jan 19, 2018 9:58 pm

rpineau wrote:
Fri Jan 19, 2018 9:44 pm
Are you still doing the clock sync we were doing on the "old" booster as these are unrelated clocks ?
Its same code as in V2.2 booster, and STE booster. But code works fine on STE up to 38MHz.. on the STFM.. nope.. refuses to work.

Really when CPU not accessing the bus, the CPU should be able to run at any speed (un-related clock) but just doesn't work.. There is nothing wrong with the 8/22mhz switching clock, looks fine..

I have removed the blitter and it seems to bring up the Atari logo more constant now, but logo is about as good as it gets. Something just isn't happy doing this :shrug: :shrug:
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS

Post by rpineau » Fri Jan 19, 2018 10:17 pm

That is weird indeed.
I'll need to think about that one. I'll ping you if I have an idea
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS

Post by exxos » Sat Jan 20, 2018 10:32 am

rpineau wrote:
Fri Jan 19, 2018 10:17 pm
That is weird indeed.
I'll need to think about that one. I'll ping you if I have an idea
Looking at my original dev-board that I was doing async tests, it looks like I could run the CPU at 16mhz all the time from the system clock, but while I got to desktop with 20mhz, I assumed ACIA overclock problem as the keyboard was malfunctioning. But maybe it wasn't the ACIA running to fast and showing up same problem I have now.. Its hard to say.

It looks like one of the main problems was I had to tri-state UDS,LDS.. These are linked direct to CPU so that could be a issue... but STE not care about that anyway.. I did not route those pins on this current V2.6 PCB (via PLD) as did not see I needed to.

I will have to hook up my dev-board again and do some more tests, I have full control over everything on that board... I can do more tests with 8/22mhz switching there... plus this time as I am not running constant speed.. I shouldn't have any ACIA timing issues..

There must be some conflict somewhere in anycase, I mean CPU held off for RAM access.. ROM is decoded on PCB.. no blitter.. so nothing should be bus master to conflict on the bus ? Maybe DMA doesn't use bus grant stuff from CPU? ROM doesn't request bus.. so maybe DMA doesn't either ? I guess I need to check if anything uses bus grant without blitter...

If anyone can test a stock STF machine to see if BGACK ever goes low it would help (no time until monday afternoon to do anymore testing now) ..
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