CURRENT PROTOTYPE STATUS (SEC 64MHz 68000)

Information and news about the 68SEC000 64MHz booster.
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by exxos » Thu Jan 23, 2020 10:31 am

75MHz!

A speed increase of 50% over 50MHz! All still on a 68000!

I redid some code last night which seems to help stability a great deal. Unfortunately I still cannot get EMUTOS or TOS206 to boot at all :(

Of course results are not much different than 32MHz since ROM speed is already maxed out. BUT, integer division shows a speed boost here (355% at 32Mhz on the STE) and more importantly it seems stable at this speed as well!

Ultimately if I could find some low-cost 25ns SRAM or faster , then that coupled with 75Mhz would really shift!

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EDIT:

I now have EMUTOS and 206 running at 64MHz.. This was down to a "delay" on A1 which I added because of some previous DMA related issues. Because A1 is going via the PLD, I wonder if even a few ns delay is causing 75Mhz not to work.. might have to get some bodge wire out...

EDIT2:
Nope, still not happy at 75Mhz.
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by exxos » Thu Jan 23, 2020 2:08 pm

TOS206 *almost* got there at 75Mhz that time... I simply added a 1.5K pull up on RESET... So at least its actually trying to boot now!

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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by IngoQ » Thu Jan 23, 2020 2:45 pm

exxos wrote:
Thu Jan 23, 2020 10:31 am
75MHz!
A speed increase of 50% over 50MHz! All still on a 68000!
Holy shit... This reminds me a little of the good old 486DX/4 days... only that yours would be a 68000DX10 by now ;)
Ingo :geek:

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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by exxos » Thu Jan 23, 2020 2:47 pm

IngoQ wrote:
Thu Jan 23, 2020 2:45 pm
Holy shit... This reminds me a little of the good old 486DX/4 days... only that yours would be a 68000DX10 by now ;)
:lol: Need to find a 80Mhz osc next :lol:
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by exxos » Thu Jan 23, 2020 4:07 pm

The good news is TOS206 is now working at 75Mhz. The bad news is.. this may need water cooling :lol: :roll:

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EDIT:

Now pushing ROM over its limits :lol:

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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by exxos » Sun Jan 26, 2020 1:56 pm

For the hell if it I tried 80MHz but its really not happy, aka row of bombs. But considering I have to keep spray freezer spray on it at 75MHz I think realistically 64MHz is likely going to be the max "safe" clock. Of course not all chips may overclock the same either.

64MHz has a 68K cycle time of about 30ns, plus say 10ns for the PLD, 40ns total. It means the ROM being 55ns can only in effect cope with 32MHz speeds anyway.

The SRAM I have been (still) waiting to be built uses 45ns chips. So I think again that 64MHz works out well in that respect. I have been talking to @terriblefire about SRAM last week. Basically because those SRAM chips I am using are like £20 a pop, 4 of them , £80, the pcbs were expensive because of being "tight".. plus other build costs, its going to push it to £120 just for 8MB fast-ram. Its just not a good solution.

As TF says, SDRAM is much cheaper, I mean its like 128MB for £1.50.. its 3.3V so will need some level shifters. TF also says he can mash us up with a xilinx SDRAM controller, so I think I can mash up a 68K sized board as before which can easily have as much RAM as needed. This SDRAM is way faster than I need for 64MHz as well. some of it is down to just 5ns!

We can actually have up to 10MB fast-ram on a 68000 I think. With a 16MB chip I could mash up some logic to copy the ROM to SDRAM on power up, so ROM runs from SDRAM instead of the ROM chip itself. This would mean 64MHz access to "ROM" instead of the current 32MHz speed.

Also the same fast-ram board could be adapted when I move over to the 020 CPU. As we have 32bit access on there, having a fast-ram board with 32bit is going to be lightning fast if we can push 64MHz on a 020. In term of the 020, its not much of a jump from the SEC design so it shouldn't be to much to get one working.. though as always, with so many projects on the go, the 020 may not even be designed until next year.

There are some other projects going on in the background relating to the H4 which mixes in with the booster stuff, so I am not sure yet which of the many directions to ultimately go in yet. I will do a 020 adaptation, but its if I spend time on the H4 related stuff more than STFM stuff which is one of the main issues. The direction may well be a 020 based H4 running at 50mhz at 32bit.. but there's a lot of work in a motherboard re-design to move it to a 020 based design.
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by pixelpusher » Sun Jan 26, 2020 2:44 pm

One question - and apologies, if this stated clearly on the Last upgrade page or in the store (and I missed it): Does the booster work with some cache, or do you focus your engineering marvels on pushing the speed (most effectively for internal cpu operations)?

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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by exxos » Sun Jan 26, 2020 2:48 pm

pixelpusher wrote:
Sun Jan 26, 2020 2:44 pm
One question - and apologies, if this stated clearly on the Last upgrade page or in the store (and I missed it): Does the booster work with some cache, or do you focus your engineering marvels on pushing the speed (most effectively for internal cpu operations)?
My focus was to push the 68000 to its limits. ROM access is done at 32MHz, internal operations are 64MHz. Caches only come into play when I move to the 020.

Even so, if you read the 16MHz mod threads, we have double clocked the ST-RAM to 200%, so it renders external caches kinda pointless anyway.
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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by pixelpusher » Sun Jan 26, 2020 3:16 pm

exxos wrote:
Sun Jan 26, 2020 2:48 pm
pixelpusher wrote:
Sun Jan 26, 2020 2:44 pm
One question - and apologies, if this stated clearly on the Last upgrade page or in the store (and I missed it): Does the booster work with some cache, or do you focus your engineering marvels on pushing the speed (most effectively for internal cpu operations)?
My focus was to push the 68000 to its limits. ROM access is done at 32MHz, internal operations are 64MHz. Caches only come into play when I move to the 020.

Even so, if you read the 16MHz mod threads, we have double clocked the ST-RAM to 200%, so it renders external caches kinda pointless anyway.
Even with 16 MHz ram speed that's just 1/4th of cpu speed (64 Mhz - or 75 in your latest installment). I recently found a "proVME 16 Mhz" booster in my storage (that I have used about 30 years ago and need to re-fit) and if memory serves me well, that got a decent boost even from its primitive direct mapped cache.

I wonder if an improvement for read operations (and overall programs naturally do much more read then write ops) wouldn't further reduce the impact of the ram bottleneck in your high clocked application too (assuming you can get a cache reasonable fast).

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Re: V2.5 BOOSTER CURRENT PROTOTYPE STATUS (SEC BOOSTER)

Post by exxos » Sun Jan 26, 2020 4:09 pm

external caches are pointless like I said.Expensive and hard to get , we looked into it years ago. 50mhz 020 internal caches will help a great deal. Running 16MHz ST-ram is just step 1, one day RAM will run at 50mhz and again it just renders caches pointless. Why bother to cache a small area of RAM when can increase the entire RAM speed ?
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