Designing PSU: PSU Curent Limit Latching issue

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kuaile
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Joined: Thu Dec 21, 2017 7:05 am

Designing PSU: PSU Curent Limit Latching issue

Post by kuaile » Thu Dec 21, 2017 7:33 am

Hi to all, I'm recently design PCU,there are questions for circuit need to solution. I have to say it's complex for me because I have no experience :oops: . The circuit below shows a part of a circuit that I am designing for a it.


The problem I have with the circuit below is that as soon as the circuit goes into Current Limit mode, it pushes V-Out up to about 8V, and I cannot recover from this, even if I set the current limit much higher than where it initially latched. The only way to recover from this is to un-plug the circuit and then reset.
Image

What I think is happening is that when we go into Current Limit mode, and Q1 turns on, OpAmp (IC3A) tries to compensate for its output being pulled to ground, and somehow drives 8V across... Actually no... If Q1 is on, surely the maximum voltage that it could show would be 0.7V, no? How is that OpAmp able to sustain more than 8V with its output shorted to ground?

Some context

I-Sense senses the Current over a shunt resistor and can be 0-3V.
I-Set comes from a DAC with an upper reference voltage of 3.0V
V-Set comes from a similar DAC with the same 3.0V reference voltage
V-Out is the input to an LT3080 Linear Voltage Regulator and could range between 0 and 30 Volts
CLIM is purely a digital input to a micro controller to let it know when we are in Current Limit mode.
Before we go into Current Limit mode, everything seems to be working as expected.

Note that I am testing this with no load but there is a 10mA current source connected to the output of the LT3080 as stated by its spec sheet to allow varying the voltage down to 0V.

Update

The Image below is what I see of Pin 1 of IC3A when the output is at about 1.7V. Is that expected? I would not have expected the pulse. Does this mean the V-Set signal is not smooth enough? Testing with a standard Arduino Mega PWM001 http://www.kynix.com/Detail/1318659/PWM001.htmlsmoothed (somewhat) with a crude single stage RC filter. IC3B is off until it latches and then goes to VCC (34V in this case) as expected.
Thanks all advice and you taking time to read.
Image

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exxos
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Re: Designing PSU: PSU Curent Limit Latching issue

Post by exxos » Thu Dec 21, 2017 9:41 am

Trying not to sound dumb here, but why use current limiting in the first place ? A lots of regulators have internal limiting, and if you need more control over it, there are a lot of IC's with internal current limit control. You could do a lot more with less bits..

There is even "current shunt monitors" where you just have a normal shunt resistor and the chip acts like a op-amp, when voltage drop gets to high, it flags a output on the chip..
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