exxos's Atari, Amiga & retro forum

stephen_usher wrote: ↑Sun Sep 27, 2020 6:49 pm @exxos What model eeprom do you use for your dualtos?

AT27C4096-55JU

Thanks.

Does this logic for the ROM decode look OK? The GAL will match the address patterns for both possible ROM address ranges.

I've used /AS for the ROM /CE as according to the spec. /CE should be enabled before /OE and given the logic delays this should work due to the logic delays in the GAL and 74LS08.

I'm using A17 on the EEPROM to switch between TOS images.

I've just noticed a mistake. The second AND gate will not work and can be left out. Though really the /OE activation on the EEPROM should require /AS to be asserted as otherwise it could be reacting to a spurious address on the bus.

OK, I'll have to use a NOR gate in an 74LS02.

Or I can use a second GAL, but that's slower.

Just a mo... The EPROM is only 256Kx16, so how do you fit two (potentially 256K) TOS images in there?!

stephen_usher wrote: ↑Sun Sep 27, 2020 10:57 pm Just a mo... The EPROM is only 256Kx16, so how do you fit two (potentially 256K) TOS images in there?!

For two tos versions you'll need something like a 27c400 or 27c4096.

I'm getting confused by the Axx notation differences between the m68k (starts at A1) and the chip (starts at A0).

I'm not really following your circuit.. You have a gal, so why external gates ? You just decode TOS206 space and do a OR type equation in the GAL for ROM2.. I am making the assumption ROM2 is the one the glue set low on address zero. Or just run all 3 ROM limes to the GAL.. Then your GAL logic will set ROM OE low on valid address range OR ROM2 for address zero decode.

You also run /AS as a condition in the GAL logic to only allow any decoding when /AS is low. Otherwise you end up with glitches on ROM OE due to his transitions etc.

As for DTACK, have the GAL set low at the same time as ROM OE, the TF536 should be able to cope with that AFAIK. In general a 8mhz CPU won't read DTACK until after 55ns (ROM access time) so DTACK speed isn't really relevant in this case.

Because I’ll not be using the standard ROM sockets I’ll have to decode the TOS 1.xx addresses too, so I need the 8 address lines into the GAL to do this. The GAL16V8 only has 8 general purpose inputs, so they’re all used up. The other two lines are more restricted, being i1/CLK and i’ve forgotten what i10 ‘s main function is.

As for /ROM2, I was basing this on the decoder DoG referenced. Yes, /ROM2 is asserted for the zero reads. Actually, looking at the Atari schematics it may also be asserted for the TOS 1.xx address space too, so that would mean I wouldn’t need the more complicated GAL logic and I could use only 6 address lines, freeing up two inputs for /AS and /ROM2.

I should really stop /ROE if /RW is low so as to cause a bus error on an attempted write to the address space.