So the Xilinx (et al) JTAG adaptors can sense the voltage level of the board in the case when the JTAG adaptor is multi voltage.
You are setting the voltage on the output side of the voltage regulator but not the input... dont do that.
So the Xilinx (et al) JTAG adaptors can sense the voltage level of the board in the case when the JTAG adaptor is multi voltage.
Gotcha. Never realised that could be a problem. I will power it off the bus for future programmings.terriblefire wrote: ↑Thu Oct 15, 2020 7:39 pm You are setting the voltage on the output side of the voltage regulator but not the input... dont do that.
From what's been posted previously I was under the impression that the firmware asserted the CDIS line for all addresses outside of the Alt-RAM address range, turning caching off for those addresses. This is important for ST-RAM, of course, as the DMA can change the data in RAM without the CPU's knowledge.exxos wrote: ↑Mon Nov 23, 2020 3:54 pm You cannot use the cache with stock 206 there is a bug in the OS.. it was talked about a few times already.. @agranlund I think did some patches to it to fix it but don't think it has been tested / released yet.. For now you have to disable the cache in the desktop menu.. or it might be easier just to run EMUTOS for now.
I can only find it mentioned in passing here https://www.exxosforum.co.uk/forum/viewt ... 276#p50284 I don't think it was ever done @agranlund ? IIRC @agranlund went to patch TOS206 to fix it properly, but I don't remember where this was discussed as we talk about stuff a lot in the private area so people dont get confused whats going on. Even so, all the Atari firmware and patches are likely all still WIP at this point. We are working on some TF536 stuff in the background, but I can't disclose what all this is currently.stephen_usher wrote: ↑Mon Nov 23, 2020 4:08 pm From what's been posted previously I was under the impression that the firmware asserted the CDIS line for all addresses outside of the Alt-RAM address range, turning caching off for those addresses. This is important for ST-RAM, of course, as the DMA can change the data in RAM without the CPU's knowledge.
TOS3.06 (and of course EmuTOS) flushes the 68030 data cache after disk operations, so they are fine, this does not happen on TOS2.06.stephen_usher wrote: ↑Mon Nov 23, 2020 4:08 pm From what's been posted previously I was under the impression that the firmware asserted the CDIS line for all addresses outside of the Alt-RAM address range, turning caching off for those addresses. This is important for ST-RAM, of course, as the DMA can change the data in RAM without the CPU's knowledge.
There are plenty to read on this subject on Amiga forumsEnabling write-allocation has an undesired side effect, though: as the NOT CIIN signal is ignored during write-accesses, a longword-aligned write of a longword will create a valid cache entry that may cause a cache hit during subsequent read accesses, regardless of the caching mode for that memory location as indicated by the external hardware. This behaviour can be corrected only by using the MMU to specify caching modes on a page-by-page basis