Smonson wrote: ↑Tue Nov 28, 2017 1:55 am
I think it would be OK to reset the shifter from one scanline to the next in a normal ST video mode, because each scanline begins on LOAD 0 and with no preexisting data in the shifter's registers. I was clearing its state on the assertion of DE before, just on the assumption that it was sensible to do so, but obviously the real shifter doesn't work like that.
Sounds like a good idea to "rest" on VSYNC. I think DE could even be low all the time in terms of overscan stuff. The amount of times DE pulses should be relative to the scan line pixel length (x4 for 4 bit planes). So I think we can rule out DE being used as any sort of "reset" system.
Smonson wrote: ↑Tue Nov 28, 2017 1:55 am
I don't understand why they would make the chip with these complex reset mechanisms that they then went on to never use. *shrug*
They wouldn't have done.. Atari I presume would be looking for quick and simple and minimal gates. So thinking towards something gets "reset" obviously isn't right here.
EDIT:
Just thinking out load.. but maybe LOAD isn't clocking the data into the shifter, but just more of a enable signal to latch data. Maybe on power up the shifter resets to count 0 and simply counts up automatically on its own each time and never drifts. The clocks between MMU and Shifter are in sync...
EDIT 2:
DE just sets the shifter to display pixels or not, DE can be tied high all the time, so nothing screws up in that signal.
LOAD must load data into the shift registers.
I assumed LOAD clocks the shifters with data, and its probably correct. Obviously there is something else here. As if we did a resolution change the LOAD cycles would be some "odd" number..and cause bit planes shits... or would they ?
We don't get bit planes shifts in general, so I can only assume the MMU completes all load cycles in any particular resolution. On this basis, we don't need to "reset" the shifter counters at all.
In terms of a system crash, this is mostly CPU.. the MMU is kinda doing its own thing with the video, regardless of what the CPU is doing. So I still think the MMU would complete a even (correct) number of LOAD pulses.
EDIT3:
Looking back at this...
- 50hz_video clock DE to load to screen latencies.png (28.51 KiB) Viewed 6048 times
DE goes HI about 8 clocks before the MMU starts loading DATA.. Maybe a clue...
If the machine powers up and DE is high all the time, then the number of LOAD pulses wouldn't change..
If the machine is running as normal, maybe DE low for more than 4 clocks is what "clocks out" the shifter data and resets the counter... Then LOAD uses to clock the count from 1-4 as normal.
Trying to think how it would work...
I mean is simply DE is LOW and LOAD is HIGH, then use that to reset the 1-4 counter.
Then when DE goes HI, the condition is false, and the counter uses LOAD to count 1-4. This would mean the counter is reset every scan line...
This would mean DE basically becomes the reset signal... I forgot what the question was now ?