Yeah, Xilinx still does 5V chips, but I don't think Altera/Intel do any more. Would need to switch ecosystem. Not sure how much is involved with that.
Let's think. If I routed all the data and address lines via the CPLD I wouldn't need level shifting, but that'd need around 114 pins! Routeing address only would need around 50 (give or take), then only level shifters for the data lines. That sounds doable, and is, I suspect, what the TF536 does.
Does Xilinx programming require specific Xilinx-compatible hardware?
Ha! Crawl before I can sprint, I think.What about some (quad)SPI expansion port for fast interfacing with some MCU based daughterboard, that would serve as gateway to USB, Ethernet, Wifi, etc..?
One of my main aims is to keep the form factor small enough that the PSU can remain in place on the Falcon, so concentrating on the core goal of memory at the moment. The acceleration is a nice side effect. Programmable ROM would be nice, but anything else I can piggyback on later would be purely bonus.
Thanks,
BW.