MSTE vs STE TOS206

[exxos]

16MHz CACHE OFF

MSTE16_result.png (4.25 KiB) Viewed 2012 times

16MHz CACHE ON

MSTE16CA_result.png (4.3 KiB) Viewed 2012 times

16MHz CACHE ON - BLITTER OFF (MSTE VS ST SPEEDS)

mstenb.jpg (102.39 KiB) Viewed 1843 times

Just for reference, ST vs ST with blitter ON.

stb.JPG (257.04 KiB) Viewed 1841 times

In terms of cache vs blitter. Blitter makes faster work than using caches. But in above tests MSTE doesn't outperform stock STE.

In terms of ROM access, It should be 200% without cache due to 16MHz speeds, but it only sees speed increase with caches enabled. So MSTE doesn't seem to be running in 16MHz for ROM access. As such GB6 tests show not much speed increase in GEM related tasks.

However, CPU related tests access using cache make much faster work. I copied bob test results from later in thread to show how caching improves CPU & RAM related routines.

Using Frank's blitter demo... viewtopic.php?f=25&t=50

16MHZ CACHE ON

Code: Select all

Blitter render                $1B bobs
CPU shift  blitter active     $11 bobs  
CPU pre-shift blitter active  $1C bobs

16MHZ CACHE OFF

Code: Select all

Blitter render                $1A bobs
CPU shift  blitter active     $0B bobs  
CPU pre-shift blitter active  $13 bobs

8MHZ CACHE OFF

Code: Select all

Blitter render                $1A  bobs
CPU shift  blitter active     $0A  bobs
CPU pre-shift blitter active  $13  bobs

Will ignore 8MHz tests as basically no difference..

So cache on vs cache off..

Code: Select all

Blitter render                 +1 bob
CPU shift  blitter active      +6 bobs
CPU pre-shift blitter active   +9 bobs

So can see CPU operations are faster because of caches.

In terms of unfair test with 40MHz STE (no caches)

Code: Select all

Blitter render                $1B bobs
CPU shift  blitter active     $0C bobs  
CPU pre-shift blitter active  $16 bobs

So results faster than stock machine

Code: Select all

Blitter render                 +1 bob
CPU shift  blitter active      +2 bobs
CPU pre-shift blitter active   +3 bobs

So we can see CPU with caches give +3 bobs( from 10 bobs to 13 bobs) and using pre-shifting, caches come into play for fast copy of data and give +9 bobs (from 19 bobs to 28 bobs) .

So conclusions are tricky with this machine. Anything using blitter in particular with GEM tasks are not showing much speeds over a stock STE. Anything which doesn't use blitter (games for example) will see a reasonable increase in speed due to caches.

[Darklord]

What am I missing here Chris? I would have thought the boost from an 020 and its
architecture would naturally be expected to be faster?

Thanks.

[exxos]

What am I missing here Chris? I would have thought the boost from an 020 and its
architecture would naturally be expected to be faster?

Has a 68000 in there according to GB6.. didn't think any MSTE had a 020 ?

[rpineau]

MSTE is a 68000, not 68020.
TOS 2.06 can work with a 68020 (and even a 68030 ).

[Darklord]

Er sorry for the confusion - was referring to Chris's comment:

" I think a 16MHz 020 would easily outperform the MSTE."

Just thought there wouldn't have been any question about it.

I wasn't implying there was an '020 in Mega STe's. I've got one,
for what it's worth.

[dhedberg]

Why does the CPU only show 124% with cache OFF? Shouldn't it be close to 200% considering the frequency is 16MHz? What more test is taken into consideration besides integer divison?

[Cyprian]

Why does the CPU only show 124% with cache OFF? Shouldn't it be close to 200% considering the frequency is 16MHz? What more test is taken into consideration besides integer divison?

I guess RAM/ROM Access is also taken into account

[Petari]

68020 CPU is faster even at same clock than 68000 - many instructions execute in less clock cycles. But there are some, not much which are slower - like interrupt handling.
Ah, and there is simple solution for slow ROM TOS execution - run it from RAM I will benchmark it today afternoon ...

[exxos]

Why does the CPU only show 124% with cache OFF? Shouldn't it be close to 200% considering the frequency is 16MHz? What more test is taken into consideration besides integer divison?

int-div is the only logical result... My V1 booster has ...



Thats a 8/16MHz switch.. the MSTE doesn't even get close to that

So either the MSTE has a very poor 8/16MHz switch, or CPU is running constant 16MHz with very poor state machine..

Seems to be its not really a 16MHz machine.. Its basically a STE with a cache giving ST-RAM a boost.. and thats pretty much it aside from 16MHz int-div test..

[Petari]

Don't like your new Mega STE exxos ? There is solution to get rid off it
I mean there is much more than + cache and 16 MHz CPU in compare to STE . For instance PSU is much-much better. Then better case, overall quality. I will not repeat what extra features and HW it has.
It has switch for CPU clock and CPU cache - HW register. And it runs then at 16 MHz, with 16 KB cache. With some waits - if data is not in cache must wait. If accessing ROM must wait. So simple. And that explains why integer division is 195% - it works most time internal, with little memory access.
And I must say that GEMbench tests are not really representative. ROM access should be exact 100% at 16 MHz. But RAM access is only 101%, lower than ROM access - and that's not realistic. Of course, real RAM access ratio depends from running SW. It may be 200% if all is in cache. Bad ROM access value is for sure because test code running from RAM, so it execs little faster, but that should be compensated - knowing that code read speed is for sure 200% - it fits in 16 KB RAM, so will execute from cache all time. If you use movem.l with all possible registers, then RAM access %-age will be very low. But even better is to make first RAM access test with known cycle times, then can compensate ROM access execution times with it.