Project: HDMI/DVI out for STFM

[exxos]

Seems plenty fast according to that spec sheet, unless I'm misunderstanding something.

I think it was just a suggestion..Nothing wrong with those of course.

For my stuff, I am pushing every MHz out of everything, so the IDT switches have pretty much zero delay, which is what I need. In case of the FPGA stuff, a few ns isn't going to make any odds. Though I guess the IDT stuff may be easier to solder as they (IIRC) are larger packages.

[poobah]

... Though I guess the IDT stuff may be easier to solder as they (IIRC) are larger packages.

Yup, I solder them by hand fairly easily.

[Smonson]

The only reason I mention the buffer is that the one I used for the 16MHz line (M74VHC1GT125DF2G) can't hack it at 32MHz. Since 16MHz is not too fast by today's standards I didn't worry about it when selecting buffers.

[rpineau]

May I suggest the NB3N551 for clock buffering :

https://www.mouser.com/datasheet/2/308/ ... -83648.pdf

[Smonson]

Suggestions are welcome. But from the datasheet it looks like this device is only guaranteeing to produce a 2.4v high. Dunno if the Atari would be too happy with that.

But this is definitely the kind of thing I should have used in the first place

[poobah]

A little overkill, but maybe this guy...
http://www.ti.com/lit/ds/symlink/cdc208.pdf


I think you could coerce some of the IDT fanouts to work as well.

[exxos]

Suggestions are welcome. But from the datasheet it looks like this device is only guaranteeing to produce a 2.4v high. Dunno if the Atari would be too happy with that.

https://www.idt.com/document/dst/qs32x2245-datasheet

Datasheet a little unclear, but it lists "pass voltage" as 4V for 5V VCC.

Where did you read 2.4v ? That doesn't sound right.

[Smonson]

https://www.idt.com/document/dst/qs32x2245-datasheet

Datasheet a little unclear, but it lists "pass voltage" as 4V for 5V VCC.

Where did you read 2.4v ? That doesn't sound right.

You've got a different datasheet there, I was talking about the NB3N551 - but I just checked again and VOH is given twice, once at 35mA where it's min. 2.4v and then again a bit further down where it's min VDD - 0.4v at 12mA, so that's a bit more like it.

I like the smallness of that one. A downside of the otherwise excellent CDC208 mentioned by Poobah is that it's really big compared to the 2x3mm chip I've got on there now.

[rpineau]

I was thinking more about using it to buffer the 32MHz from the ST to the FPGA so that the frequency can be exact and work for the demo stuff.
I have put one of this on the new rev of our 68020 board (still not assembled one of the new one) but haven't tested it.
I think the actual Hi level is VDD – 0.4. I'm not sure what the 2.4V represents in the datasheet.

[Smonson]

I was thinking more about using it to buffer the 32MHz from the ST to the FPGA so that the frequency can be exact and work for the demo stuff.
I have put one of this on the new rev of our 68020 board (still not assembled one of the new one) but haven't tested it.
I think the actual Hi level is VDD – 0.4. I'm not sure what the 2.4V represents in the datasheet.

It's probably just being pulled down by the high current, 35mA must be near the maximum it's intended to supply.

Unfortunately the FPGA on my shifter board is running at 3.3v, so this particular device wouldn't be able to act as a level converter in that direction (max input voltage is 3.8v when running on 3.3v supply). Maybe a resistor divider would work to reduce the voltage?