Project: HDMI/DVI out for STFM

Progress on our FPGA cores.
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Re: Project: HDMI/DVI out for STFM

Post by exxos » Thu Nov 22, 2018 12:31 pm

My board is still hooked up to my STFM on the floor if it helps... Not done anything much with it as been to busy with other things :(
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Re: Project: HDMI/DVI out for STFM

Post by Smonson » Thu Nov 22, 2018 1:33 pm

exxos wrote:
Thu Nov 22, 2018 12:31 pm
... been to busy with other things :(
I understand completely, believe me :D

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Re: Project: HDMI/DVI out for STFM

Post by Smonson » Sat Nov 24, 2018 4:09 am

Well, it's obvious that the real shifter drives the data bus only for the duration of CS, which is what I originally thought.

(CS at the top, D1 at the bottom with a pulldown resistor - shifter is running at 1MHz instead of 32)
DS0005.png
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Re: Project: HDMI/DVI out for STFM

Post by Smonson » Fri Nov 30, 2018 8:27 am

Icky has generously donated his time to investigate the weird register reading behaviour with his oscilloscope. This image collects the most important signals into one graphic. I cannot, for the life of me, see where the problem is coming from or how it's possible. If anyone has any theories I'd love to hear them.

For each scope screen, the top trace is /CS, and is the common factor keeping all these screenshots synchronised with each other.

The test program from a few posts above is running, and it just sits in a loop reading register 0xFF8260 (with vblank vector disabled so that TOS doesn't interfere). So each time CS is low, that's the program reading the shifter's resolution register. The value actually being output on the bus by the shifter is all zeroes.

My (unconfirmed) understanding of how the register is read is this:
  • The MMU asserts /CS to get the shifter to drive the data bus
  • The MMU then raises, then lowers LATCH which allows the 74LS373 latch ICs to latch the values that it sees on D0-D15. Setup and hold time for the '373s is 20ns, which is satisfied.
  • At some point later, the MMU asserts RDAT, (which is /OE for the '373s, output enable) to drive the same signals onto the 68000 bus to be read.
This last point is not depicted on the diagrams. I didn't ask Icky to look at these ones because the shifter isn't involved.

My observations:
  • The latching behaviour is only level-sensitive, so high-frequency noise around the transitions shouldn't cause glitches
  • The values that are being read seem very non-random, in the sense that either reads the whole word perfectly, or else it reads it with 8-12 wrong bits. It never reads just one wrong bit here and there. The pattern of bits is also very uniform, e.g. 0xb479 comes up a lot (see video and screenshot posted by Icky above)
  • The reason I don't think it's clock related is that both Icky and Troed have the same behaviour, and Troed is using a totally different clock.
collected.png
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Re: Project: HDMI/DVI out for STFM

Post by exxos » Fri Nov 30, 2018 10:12 am

Where's the test program ?
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Re: Project: HDMI/DVI out for STFM

Post by Smonson » Fri Nov 30, 2018 10:29 am


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Re: Project: HDMI/DVI out for STFM

Post by exxos » Fri Nov 30, 2018 10:47 am

Program doesn't seem to be doing anything ?

IMG_3627.JPG
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Re: Project: HDMI/DVI out for STFM

Post by exxos » Fri Nov 30, 2018 10:53 am

Tried in medium res..

now just stuck on this...

IMG_3628.JPG
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Re: Project: HDMI/DVI out for STFM

Post by Smonson » Fri Nov 30, 2018 11:08 am

Doing nothing is good, it means it's only reading zeroes (or 1 in medium). Like me, your machine works with the mod for some unknown reason.

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Re: Project: HDMI/DVI out for STFM

Post by exxos » Fri Nov 30, 2018 11:15 am

I removed the cap I added and this is what happens to the video...

( still get nothing in that program with the cap removed)




IMG_3630.JPG
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Video is fine with the cap.
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